PIC18F8620-I/PT Microchip Technology, PIC18F8620-I/PT Datasheet - Page 14

• Manufacturer Part Number: PIC18F8620-I/PT
• Description: IC MCU FLASH 32KX16 EE 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8620-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 68
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.75KB
• Cpu Speed: 25MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3840 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / Rohs Status: Details

PIC18FXX20
3.2.1
The programming example presented in Section 3.2
utilizes multi-panel programming. This technique
greatly decreases the total amount of time necessary to
completely program a device and is the recommended
method of completely programming a device.
There may be situations, however, where it is
advantageous to limit writes to a single panel. In such
cases, the user only needs to disable the multi-panel
write feature of the device by appropriately configuring
the programming control register located at 3C0006h.
The single panel that will be written will automatically
be enabled based on the value of the Table Pointer.
3.2.2
All of the programming examples up to this point have
assumed that the device has been bulk erased prior to
programming (see Section 3.1). It may be the case,
however, that the user wishes to modify only a section
of an already programmed device.
The minimum amount of data that can be written to the
device is 8 bytes. This is accomplished by placing the
device in Single Panel Write mode (see Section 3.2.1),
loading the 8-byte write buffer for the panel, and then
initiating a write sequence. In this case, however, it is
assumed that the address space to be written already
has data in it (i.e., it is not blank).
DS39583C-page 14
Note:
Even though multi-panel writes are dis-
abled, the user must still fill the 8-byte write
buffer for the given panel.
SINGLE PANEL PROGRAMMING
MODIFYING CODE MEMORY
The minimum amount of code memory that may be
erased at a given time is 64 bytes. Again, the device
must be placed in Single Panel Write mode. The
EECON1 register must then be used to erase the
64-byte target space prior to writing the data.
When using the EECON1 register to act on
code memory, the EEPGD bit must be set
(EECON1<7> = 1) and the CFGS bit must be cleared
(EECON1<6> = 0). The WREN bit must be set
(EECON1<2> = 1) to enable writes of any sort (e.g.,
erases), and this must be done prior to initiating a
write sequence. The FREE bit must be set
(EECON1<4> = 1) in order to erase the program
space being pointed to by the Table Pointer. The
erase sequence is initiated by the setting the WR bit
(EECON1<1> = 1). It is strongly recommended that
the WREN bit be set only when absolutely necessary.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
and then AAh, immediately prior to asserting the WR bit
in order for the write to occur.
The erase will begin on the falling edge of the 4th
SCLK, after the WR bit is set. After the erase sequence
terminates, SCLK must still be held low for the time
specified by parameter #P10 to allow high voltage
discharge of the memory array.
 2010 Microchip Technology Inc.