PIC18F8620-I/PT Microchip Technology, PIC18F8620-I/PT Datasheet - Page 20

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PIC18F8620-I/PT

Manufacturer Part Number
PIC18F8620-I/PT
Description
IC MCU FLASH 32KX16 EE 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F8620-I/PT

Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Controller Family/series
PIC18
No. Of I/o's
68
Eeprom Memory Size
1024Byte
Ram Memory Size
3.75KB
Cpu Speed
25MHz
No. Of Timers
5
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
68
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F8620-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F8620-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18FXX20
4.0
4.1
Code memory is accessed one byte at a time via the
4-bit command, ‘1001’ (Table Read, post-increment).
The contents of memory pointed to by the Table Pointer
(TBLPTRU:TBLPTRH:TBLPTRL) are loaded into the
Table Latch and then serially output on SDATA.
TABLE 4-1:
FIGURE 4-1:
DS39583C-page 20
Step 1: Set Table Pointer.
Step 2: Read memory into Table Latch and then shift out on SDATA, LSb to MSb.
SCLK
SDATA
Command
0000
0000
0000
0000
0000
0000
1001
4-Bit
READING THE DEVICE
Read Code Memory, ID Locations,
and Configuration Bits
1
1
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
00 00
READ CODE MEMORY SEQUENCE
2
0
3
Data Payload
TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)
0
4
1
P5
SDATA = Input
1
2
3
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
TBLRD *+
4
5
6
7
8
P6
The 4-bit command is shifted in LSb first. The Table
Read is executed during the next 8 clocks, then shifted
out on SDATA during the last 8 clocks, LSb to MSb. A
delay of P6 must be introduced after the falling edge of
the 8th SCLK of the operand to allow SDATA to
transition from an input to an output. During this time,
SCLK must be held low (see Figure 4-1). This operation
also increments the Table Pointer by one, pointing to the
next byte in code memory for the next read.
This technique will work to read any memory in the
000000h to 3FFFFFh address space, so it also applies
to the reading of the ID and Configuration registers.
9
LSb
P14
10
1
Core Instruction
11
2
SDATA = Output
12
Shift Data Out
3
13
4
14
5
15
 2010 Microchip Technology Inc.
6
16
MSb
P5A
Fetch Next 4-bit Command
1
SDATA = Input
n
2
n
3
n
4
n

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