AT91SAM7L128-CU Atmel, AT91SAM7L128-CU Datasheet - Page 537
AT91SAM7L128-CU
Manufacturer Part Number
AT91SAM7L128-CU
Description
MCU ARM7 128K HS FLASH 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7L64-CU.pdf
(564 pages)
Specifications of AT91SAM7L128-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
36MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.55 V ~ 1.8 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
6 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
80
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7L128-CU
Manufacturer:
Atmel
Quantity:
2 660
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35.5
Table 35-22. Phase Lock Loop Characteristics
Note:
35.6
Table 35-23. Channel Conversion Time and ADC Clock
Notes:
Table 35-24. External Voltage Reference Input
6257A–ATARM–20-Feb-08
Symbol
Vdd
F
F
I
Parameter
ADC Clock Frequency
ADC Clock Frequency
Startup Time
Track and Hold Acquisition Time
Conversion Time
Throughput Rate
Parameter
ADVREF Input Voltage Range
ADVREF Average Current
Current Consumption on VDDCORE
PLL
OUT
IN
PLL Characteristics
Startup time depends on PLL RC filter. A calculation tool is provided by Atmel.
ADC Characteristics
1. Corresponds to 13 clock cycles at 6 MHz: 3 clock cycles for track and hold acquisition time and 10 clock cycles for
2. Corresponds to 15 clock cycles at 10 MHz: 5 clock cycles for track and hold acquisition time and 10 clock cycles for
conversion.
conversion
Parameter
Supply Voltage
Output Frequency
Input Frequency
Current Consumption
The user can drive ADC input with impedance up to:
with SHTIM (Sample and Hold Time register) expressed in ns and Z
• Z
• Z
OUT
OUT
≤ (SHTIM -440) x 20 in 8-bit resolution mode
≤ (SHTIM -550) x 16.6 in 10-bit resolution mode
Conditions
ADC Clock = 6MHz
Conditions
10-bit resolution mode
8-bit resolution mode
Return from Idle Mode
ADC Clock = 6MHz
ADC Clock = 10MHz
ADC Clock = 6MHz
ADC Clock = 10MHz
Conditions
Supplied by VDDCORE
Connected to SCLK
Active mode @ 20MHz @1.8V
Active mode @ 30MHz @1.8V
Active mode @ 40MHz @1.8V
Standby mode
AT91SAM7L128/64 Preliminary
1.60
Min
18
20
1.65
Min
Min
500
0.005
Typ
445
490
535
30
30
Typ
1.8
OUT
Typ
expressed in ohms.
Max
505
555
605
0.5
47
44
VDDCORE
Max
250
460
660
2.2
Max
1.67
10
15
6
1
(1)
(2)
MHz
Unit
KHz
µA
µA
V
Units
kSPS
Units
MHz
MHz
mA
µs
ns
µs
µA
V
537
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