AT91SAM9XE128-QU Atmel, AT91SAM9XE128-QU Datasheet
AT91SAM9XE128-QU
Specifications of AT91SAM9XE128-QU
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AT91SAM9XE128-QU Summary of contents
Page 1
... One 32-Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed – One 32-Kbyte (for AT91SAM9XE256 and AT91SAM9XE512) or 16-Kbyte (for AT91SAM9XE128) Internal SRAM, Single-cycle Access at Maximum Matrix Speed – 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128, AT91SAM9XE256 or AT91SAM9XE512 Respectively. Organized in 256, 512 or 1024 Pages of 512 Bytes Respectively. ...
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... High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2 • Two Two-wire Interfaces (TWI) – Master, Multi-master and Slave Mode Operation – General Call Supported in Slave Mode – Connection to PDC Channel to Optimize Data Transfers in Master Mode Only AT91SAM9XE128/256/512 Preliminary 2 ™ Compliant ® Infrared Modulation/Demodulation, Manchester Encoding/Decoding ...
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... Built-in lock bits a security bit and MMU protect the firmware from accidental overwrite and preserve its confidentiality. The AT91SAM9XE128/256/512 embeds an Ethernet MAC, one USB Device Port, and a USB Host Controller. It also integrates several standard peripherals, like six UARTs, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and a MultiMedia/SD Card Interface ...
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... AT91SAM9XE128/256/512 Block Diagram The block diagram shows all the features for the 217-LFBGA package. Some functions are not accessible in the 208-PQFP package and the unavailable pins are highlighted in on PIO Controller A” on page PIO Controller C” on page defines all the multiplexed and not multiplexed pins not available in the 208-PQFP package. ...
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... Figure 2-1. AT91SAM9XE128/256/512 Block Diagram 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary Filter 5 ...
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... TCK Test Clock TDI Test Data In TDO Test Data Out TMS Test Mode Select JTAGSEL JTAG Selection RTCK Return Test Clock AT91SAM9XE128/256/512 Preliminary 6 gives details on the signal name classified by peripheral. Active Type Level Power Supplies Power Power Power Power Power Power ...
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... External Wait Signal NCS0 - NCS7 Chip Select Lines NWR0 - NWR3 Write Signal NRD Read Signal NWE Write Enable NBS0 - NBS3 Byte Mask Signal 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary Active Type Level Flash Memory Input High Reset/Test I/O Low Input Debug Unit - DBGU ...
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... RTSx USARTx Request To Send CTSx USARTx Clear To Send DTR0 USART0 Data Terminal Ready DSR0 USART0 Data Set Ready DCD0 USART0 Data Carrier Detect RI0 USART0 Ring Indicator AT91SAM9XE128/256/512 Preliminary 8 Active Reference Type Level CompactFlash Support Output Low VDDIOM Output Low VDDIOM ...
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... USB Host Port A Data - HDPB USB Host Port B Data + HDMB USB Host Port B Data + DDM USB Device Port Data - DDP USB Device Port Data + 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary Active Type Level Synchronous Serial Controller - SSC Output Input I/O I/O I/O ...
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... I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Inter- face signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the peripheral multiplexing tables. 2. Refer to PIO Multiplexing (see AT91SAM9XE128/256/512 Preliminary 10 Active Type ...
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... Package and Pinout The AT91SAM9XE128/256/512 is available in a 208-pin PQFP Green package (0.5mm pitch 217-ball LFBGA Green package (0.8 mm ball pitch). 4.1 208-pin PQFP Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Character- istics” of the product datasheet. ...
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... ERASE 92 41 OSCSEL 93 42 TST 94 43 JTAGSEL 95 44 GNDBU 96 45 XOUT32 97 46 XIN32 98 47 VDDBU 99 48 WKUP 100 AT91SAM9XE128/256/512 Preliminary 12 Signal Name Pin Signal Name GND 105 RAS DDM 106 D0 DDP 107 D1 PC13 108 D2 PC11 109 D3 PC10 110 D4 PC14 111 D5 PC9 ...
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... VDDIOP0 104 4.3 217-ball LFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Character- istics” of the product datasheet. Figure 4-2. 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary Signal Name Pin CFIOW/NBS3/NWR3 153 CFIOR/NBS1/NWR1 154 SDCS/NCS1 155 CAS 156 shows the orientation of the 217-ball LFBGA package ...
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... H9 C10 NANDOE H10 C11 PC9 H14 C12 PC12 H15 C13 DDP H16 C14 HDMB H17 C15 NC J1 C16 VDDIOP0 J2 AT91SAM9XE128/256/512 Preliminary 14 Signal Name Pin Signal Name A5 J14 TDO GND J15 PB19 A10 J16 TDI GND J17 PB16 VDDCORE K1 PC24 GND K2 PC20 ...
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... Power Considerations 5.1 Power Supplies The AT91SAM9XE128/256/512 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.65V and 1.95V, 1.8V nominal. • VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and 1 ...
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... Standard ARM v4 and v5 Memory Management Unit (MMU) – Access Permission for Sections – Access Permission for large pages and small pages can be specified separately for – 16 embedded domains • Bus Interface Unit (BIU) AT91SAM9XE128/256/512 Preliminary 16 each quarter of the page 6254CS–ATARM–08-Jan-10 ...
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... Allows Handling of Dynamic Exception Vectors 7.2.1 Matrix Masters The Bus Matrix of the AT91SAM9XE128/256/512 manages six Masters, thus each master can perform an access concurrently with others, depending on whether the slave it accesses is available. Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings ...
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... Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface – Two for the Two Wire Interface – One for Multimedia Card Interface – One for Analog To Digital Converter AT91SAM9XE128/256/512 Preliminary 18 List of Bus Matrix Slaves Internal SRAM Internal ROM ...
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... Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary 19 ...
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... Memories Figure 8-1. AT91SAM9XE128/256/512 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI 256M Bytes ...
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... The embedded ROM contains the Fast Flash Programming and the SAM-BA boot programs. Each of these two programs is stored on 16-Kbyte Boundary of FFPI and the program executed 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary Table 8-3, “Internal Memory Mapping,” on page 25 Figure 8-1 on page for details. ...
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... PGMNOE PGMNVALID PGMM[3:0] PGMD[15:0] ® 8.1.4.2 SAM-BA Boot Assistant The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in situ the on-chip Flash memory. AT91SAM9XE128/256/512 Preliminary 22 0x0000 0000 SAM-BA Program 0x0000 3FFF TST=0 Signal Description PIO Type PA0 ...
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... The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). 8.1.5 Embedded Flash The Flash of the AT91SAM9XE128/256/512 is organized in 256/512/1024 pages of 512 bytes directly connected to the 32-bit internal bus. Each page contains 128 words. The Flash contains a 512-byte write buffer allowing the programming of a page. This buffer is write-only as 128 32-bit words, and accessible all along the 1-Mbyte address space, so that each word can be written at its final address ...
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... FFFF or 0x0023 FFFF or 0x0027 FFFF 8.1.5.3 GPNVM Bits The AT91SAM9XE128/256/512 features four GPNVM bits that can be cleared or set respec- tively through the commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface. Table 8-2. GPNVMBit[#] 8.1.5.4 ...
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... Auto baudrate detection • SAM-BA Boot in case no valid program is detected in external NVM, supporting – Serial communication on a DBGU – USB Device Port 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary summarizes the Internal Memory Mapping for each Master, depending on the Remap Internal Memory Mapping REMAP = 0 Address ...
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... Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode supported AT91SAM9XE128/256/512 Preliminary 26 Figure 8-1 on page 20. 6254CS–ATARM–08-Jan-10 ...
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... The purpose of this control is to adapt the signal to the frequency. Two bits enable the user to select High or Low Drive for memory data/addresses/control signals. Setting the EBI_DRIVE field [17:16] in the EBI Chip Select Assignement Register (EBI_CSA) located in the Chip Select Interface of the Bus Matrix, enables control of the EBI. 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary 27 ...
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... System Controller can be addressed from a single pointer by using the stan- dard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 Kbytes. Figure 9-1 on page 29 Figure 8-1 on page 20 peripherals. AT91SAM9XE128/256/512 Preliminary 28 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller 6254CS–ATARM–08-Jan-10 ...
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... System Controller Block Diagram Figure 9-1. AT91SAM9XE128/256/512 System Controller Block Diagram periph_irq[2..24] efc2_irq pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset BOD VDDCORE VDDCORE POR NRST VDDBU VDDBU POR backup_nreset SHDN WKUP RC OSC OSCSEL SLOW XIN32 CLOCK OSC XOUT32 ...
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... At reset the NRST pin is an output 9.3 Brownout Detector and Power-on Reset The AT91SAM9XE128/256/512 embeds one brownout detection circuit and power-on reset cells. The power-on reset are supplied with and monitor VDDCORE and VDDBU. Signals (flash_poe and flash_wrdis) are provided to the Flash to prevent any code corruption during power-up or power-down sequences or if brownouts occur on the VDDCORE power supply ...
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... Real-time Timer with 32-bit free-running back-up counter • Integrates a 16-bit programmable prescaler running on slow clock • Alarm Register capable to generate a wake-up of the system through the Shutdown Controller 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary processor stopped waiting for an interrupt ® ® /WindowsCE ...
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... Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from AT91SAM9XE128/256/512 Preliminary 32 enabled processor Generator the ARM Processor’ ...
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... Chip Identification • Chip ID: – 0x329AA3A0 for the SAM9XE512 – 0x329A93A0 for the SAM9XE256 – 0x329973A0 for the SAM9XE128 • JTAG ID: 05B1_C03F • ARM926 TAP ID: 0x0792603F 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary 33 ...
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... Peripheral Identifier The AT91SAM9XE128/256/512 embeds a wide range of peripherals. Peripheral Identifiers of the AT91SAM9XE128/256/512. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1. ...
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... IDs. 10.3 Peripheral Signals Multiplexing on I/O Lines The AT91SAM9XE128/256/512 features 3 PIO controllers, PIOA, PIOB, PIOC, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions The multiplexing tables in the following sections define how the I/O lines of peripherals A and B are multiplexed on the PIO Controllers. The two columns “ ...
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... PA27 TIOA1 ERXCK PA28 TIOA2 ECRS PA29 SCK1 ECOL (1) PA30 SCK2 RXD4 (1) PA31 SCK0 TXD4 Note: 1. Not available in the 208-lead PQFP package. AT91SAM9XE128/256/512 Preliminary 36 Reset Power Comments State Supply I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 ...
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... RI0 PB26 RTS0 PB27 CTS0 PB28 RTS1 PB29 CTS1 PB30 PCK0 PB31 PCK1 Note: 1. Not available in the 208-lead PQFP package. 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary Peripheral B Comments Reset State TIOA3 I/O TIOB3 I/O TIOA4 I/O TIOA5 I/O I/O I/O TCLK1 I/O ...
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... PC25 D25 PC26 D26 PC27 D27 PC28 D28 PC29 D29 PC30 D30 PC31 D31 Note: 1. Not available in the 208-lead PQFP package. AT91SAM9XE128/256/512 Preliminary 38 Application Usage Comments Reset State Power Supply AD0 I/O VDDANA AD1 I/O VDDANA AD2 I/O VDDANA AD3 I/O ...
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... Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary peripherals Sensors and data per chip select 39 ...
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... MCI has two slot, each supporting – One slot for one MultiMediaCard bus ( cards) or – One SD Memory Card • Support for stream, block and multi-block data read and write AT91SAM9XE128/256/512 Preliminary TDM Buses, Magnetic Card Reader, etc.) 6254CS–ATARM–08-Jan-10 ...
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... Support for ITU-R BT.656-4 SAV and EAV synchronization • Vertical and horizontal resolutions up to 2048 x 2048 • Preview Path up to 640*480 • Support for packed data formatting for YCbCr 4:2:2 formats • Preview scaler to generate smaller size image 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary 41 ...
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... Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Four analog inputs shared with digital signals AT91SAM9XE128/256/512 Preliminary 42 6254CS–ATARM–08-Jan-10 ...
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... Package Drawings Figure 11-1. 208-pin PQFP Package Drawing 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary 43 ...
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... Figure 11-2. 217-ball LFBGA Package Drawing AT91SAM9XE128/256/512 Preliminary 44 6254CS–ATARM–08-Jan-10 ...
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... AT911SAM9XE128/256/512 Ordering Information Table 12-1. AT91SAM9XE128/256/512 Ordering Information Ordering Code AT91SAM9XE128-QU AT91SAM9XE128-CU AT91SAM9XE256-QU AT91SAM9XE256-CU AT91SAM9XE512-QU AT91SAM9XE512-CU 6254CS–ATARM–08-Jan-10 AT91SAM9XE128/256/512 Preliminary Package Package Type PQFP208 Green BGA217 Green PQFP208 Green BGA217 Green PQFP208 Green BGA217 Green Temperature Operating Range Industrial -40°C to 85°C Industrial -40° ...
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... Table 3-1, “Signal Description removed. Cross reference referring to PIO Multiplexing added to these signals. Table 10-3, “Multiplexing on PIO Controller Table 10-4, “Multiplexing on PIO Controller Section 8-1 “AT91SAM9XE128/256/512 Memory Section 6.1 “ERASE Pin”, ERASE pin is powered by VDDIOP0 rail. Section 7.2.2 “Matrix Slaves” ...
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... AT91SAM9XE128/256/512 Preliminary 47 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...