AT91SAM7XC512-CU Atmel, AT91SAM7XC512-CU Datasheet - Page 523

• Manufacturer Part Number: AT91SAM7XC512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7XC512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: MII, SPI, TWI
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7XC-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7XC-EK - KIT EVAL FOR AT91SAM7XC256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1 = Both AES_TCR and AES_TNCR have a value of 0.
Note:
• URAD: Unspecified Register Access Detection Status
0 = No unspecified register access has been detected since the last SWRST.
1 = At least one unspecified register access has been detected since the last SWRST.
URAD bit is reset only by the SWRST bit in the AES_CR control register.
• URAT: Unspecified Register Access Type:
Only the last Unspecified Register Access Type is available through the URAT field.
URAT field is reset only by the SWRST bit in the AES_CR control register.
6209F–ATARM–17-Feb-09
0
0
0
0
1
1
This flag must be used only in PDC mode with LOD bit set.
others
URAT
0
0
1
1
0
0
0
1
0
1
0
1
Description
Input Data Register written during the data processing in PDC mode.
Output Data Register read during the data processing.
Mode Register written during the data processing.
Output Data Register read during the sub-keys generation.
Mode Register written during the sub-keys generation.
Write-only register read access.
Reserved
AT91SAM7XC512/256/128 Preliminary
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