P89LPC936FDH,518 NXP Semiconductors, P89LPC936FDH,518 Datasheet - Page 66

• Manufacturer Part Number: P89LPC936FDH,518
• Description: IC 80C51 MCU FLASH 16K 28TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC936FDH,518

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 28-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 26
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC9x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 2
• Operating Supply Voltage: 21 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 8-bit
• On-chip Dac: 2-ch x 8-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1014 - BOARD FOR LPC9XX TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDMCB900K - BOARD PROTOTYPE NXP 89LPC9EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART622-1002 - USB IN-CIRCUIT PROG LPC9XX568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4339-2; 935277841518; P89LPC936FDH-T; P89LPC936FDH-T

NXP Semiconductors
Table 14.
V
T
P89LPC933_934_935_936
Product data sheet
Symbol
t
t
t
VR
RH
RL
amb
Fig 30. SPI slave timing (CPHA = 1)
DD
= 2.4 V to 3.6 V, unless otherwise specified.
= −40 °C to +85 °C for industrial, −40 °C to +125 °C for extended, unless otherwise specified.
Dynamic characteristics, ISP entry mode
Parameter
RST delay from V
RST HIGH time
RST LOW time
(CPOL = 0)
(CPOL = 1)
12.2 ISP entry mode
SPICLK
SPICLK
(output)
(input)
(input)
(input)
MISO
MOSI
t
SPIA
SS
Fig 31. ISP entry timing
t
SPILEAD
t
t
DD
SPIOH
SPIF
t
not defined
t
SPIF
SPIDV
active time
V
t
t
RST
SPICLKH
SPICLKL
All information provided in this document is subject to legal disclaimers.
t
DD
SPIF
t
SPIDSU
slave MSB/LSB out
MSB/LSB in
T
SPICYC
Rev. 8 — 12 January 2011
Conditions
t
SPIOH
t
t
t
SPICLKH
t
SPICLKL
SPIDV
SPIDH
8-bit microcontroller with accelerated two-clock 80C51 core
t
SPIR
t
VR
t
RL
t
SPIR
t
RH
P89LPC933/934/935/936
t
SPIOH
t
SPIDV
Min
50
1
1
t
SPIDSU
slave LSB/MSB out
LSB/MSB in
Typ
-
-
-
t
t
SPIDH
SPILAG
002aaa911
002aaa912
t
SPIR
Max
-
32
-
© NXP B.V. 2011. All rights reserved.
t
SPIDIS
Unit
μs
μs
μs
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