P89V51RC2FBC,557 NXP Semiconductors, P89V51RC2FBC,557 Datasheet - Page 43

• Manufacturer Part Number: P89V51RC2FBC,557
• Description: IC 80C51 MCU FLASH 32K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V51RC2FBC,557

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: P89V5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Package: 44TQFP
• Device Core: 80C51
• Family Name: 89V
• Maximum Speed: 40 MHz
• For Use With: 622-1017 - BOARD 44-ZIF PLCC SOCKET622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-2429; 935277725557; P89V51RC2FBC

NXP Semiconductors
P89V51RB2_RC2_RD2_5
Product data sheet
Fig 17. SPI master-slave interconnection
CLOCK GENERATOR
SPI
clock output and input for the master and slave modes, respectively. The SPI clock
generator will start following a write to the master devices SPI data register. The written
data is then shifted out of the MOSI pin on the master device into the MOSI pin of the
slave device. Following a complete transmission of one byte of data, the SPI clock
generator is stopped and the SPIF flag is set. An SPI interrupt request will be generated if
the SPI Interrupt Enable bit (SPIE) and the Serial Port Interrupt Enable bit (ES) are both
set.
An external master drives the Slave Select input pin, SS/P1[4], low to select the SPI
module as a slave. If SS/P1[4] has not been driven low, then the slave SPI unit is not
active and the MOSI/P1[5] port can also be used as an input port pin.
CPHA and CPOL control the phase and polarity of the SPI clock.
show the four possible combinations of these two bits.
Table 28.
Bit addressable; Reset source(s): any reset; Reset value: 0000 0000B
Table 29.
Bit
7
6
5
4
3
Bit
Symbol
8-BIT SHIFT REGISTER
MSB master LSB
SPCR - SPI control register (address D5H) bit allocation
SPCR - SPI control register (address D5H) bit description
Symbol
SPIE
SPE
DORD
MSTR
CPOL
SPIE
7
Rev. 05 — 12 November 2009
SPE
6
Description
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPI enable bit. When set enables SPI.
Data transmission order. 0 = MSB first; 1 = LSB first in data
transmission.
Master/slave select. 1 = master mode, 0 = slave mode.
Clock polarity. 1 = SPICLK is high when idle (active LOW),
0 = SPICLK is low when idle (active HIGH).
MISO
MOSI
SPICLK
SS
V
DD
DORD
5
SPICLK
V
MISO
MOSI
SS
MSTR
SS
P89V51RB2/RC2/RD2
4
8-bit microcontrollers with 80C51 core
CPOL
3
8-BIT SHIFT REGISTER
MSB slave LSB
CPHA
2
Figure 18
© NXP B.V. 2009. All rights reserved.
SPR1
002aaa528
1
and
Figure 19
SPR0
43 of 80
0