P89LV51RD2BBC,557 NXP Semiconductors, P89LV51RD2BBC,557 Datasheet - Page 76

• Manufacturer Part Number: P89LV51RD2BBC,557
• Description: IC 80C51 MCU FLASH 64K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89LVr

Specifications of P89LV51RD2BBC,557

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P89LV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Cpu Family: 89LV
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1017 - BOARD 44-ZIF PLCC SOCKET622-1008 - BOARD FOR LPC9103 10-HVSON622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1289; 935274177557; P89LV51RD2BBC

NXP Semiconductors
15. Contents
1
2
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
6.6.8
6.6.9
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . 10
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Special function registers . . . . . . . . . . . . . . . . 10
Memory organization . . . . . . . . . . . . . . . . . . . 14
Flash program memory bank selection. . . . . . 14
Power-on reset code execution. . . . . . . . . . . . 14
Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 15
Brownout detect reset. . . . . . . . . . . . . . . . . . . 15
Watchdog reset. . . . . . . . . . . . . . . . . . . . . . . . 16
Data RAM memory . . . . . . . . . . . . . . . . . . . . . 16
Expanded data RAM addressing . . . . . . . . . . 16
Dual data pointers. . . . . . . . . . . . . . . . . . . . . . 19
Flash memory IAP . . . . . . . . . . . . . . . . . . . . . 20
Flash organization . . . . . . . . . . . . . . . . . . . . . 20
Boot block (block 1) . . . . . . . . . . . . . . . . . . . . 20
ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Using ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Using the serial number . . . . . . . . . . . . . . . . . 25
IAP method . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . 27
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Capture mode . . . . . . . . . . . . . . . . . . . . . . . . . 32
Auto-reload mode (up or down counter) . . . . . 33
Programmable clock-out . . . . . . . . . . . . . . . . . 35
Baud rate generator mode . . . . . . . . . . . . . . . 35
Summary of baud rate equations . . . . . . . . . . 37
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 39
More about UART mode 1 . . . . . . . . . . . . . . . 39
More about UART modes 2 and 3 . . . . . . . . . 39
Multiprocessor communications . . . . . . . . . . . 40
Automatic address recognition . . . . . . . . . . . . 40
6.7
6.7.1
6.7.2
6.8
6.9
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
6.10
6.11
6.12
6.12.1
6.12.2
6.13
6.13.1
6.13.2
7
8
9
9.1
10
11
12
13
13.1
13.2
13.3
13.4
14
15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]
P89LV51RB2/RC2/RD2
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 62
Static characteristics . . . . . . . . . . . . . . . . . . . 62
Dynamic characteristics . . . . . . . . . . . . . . . . . 65
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 71
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 73
Revision history . . . . . . . . . . . . . . . . . . . . . . . 74
Legal information . . . . . . . . . . . . . . . . . . . . . . 75
Contact information . . . . . . . . . . . . . . . . . . . . 75
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SPI description . . . . . . . . . . . . . . . . . . . . . . . . 42
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 45
PCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PCA capture mode. . . . . . . . . . . . . . . . . . . . . 50
16-bit software timer mode. . . . . . . . . . . . . . . 51
High-speed output mode . . . . . . . . . . . . . . . . 52
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PCA watchdog timer . . . . . . . . . . . . . . . . . . . 54
Security bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Interrupt priority and polling sequence . . . . . . 55
Power-saving modes . . . . . . . . . . . . . . . . . . . 58
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Power-down mode . . . . . . . . . . . . . . . . . . . . . 59
System clock and clock options . . . . . . . . . . . 60
Clock input options and recommended
capacitor values for oscillator . . . . . . . . . . . . . 60
Clock doubling option . . . . . . . . . . . . . . . . . . . 60
Explanation of symbols . . . . . . . . . . . . . . . . . 66
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 75
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8-bit microcontrollers with 80C51 core
Document identifier: P89LV51RB2_RC2_RD2_5
Date of release: 15 December 2009
All rights reserved.