LPC2460FBD208,551 NXP Semiconductors, LPC2460FBD208,551 Datasheet - Page 390
LPC2460FBD208,551
Manufacturer Part Number
LPC2460FBD208,551
Description
IC ARM7 MCU ROMLESS 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FBD208,551
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4259
935282455551
LPC2460FBD208-S
935282455551
LPC2460FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FBD208,551
Manufacturer:
NXP
Quantity:
180
Company:
Part Number:
LPC2460FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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3. Interfaces
Table 359. USB OTG port pins
UM10237_4
User manual
Pin name
V
Port U1
USB_D+1
USB_D − 1
USB_CONNECT1 O
USB_UP_LED1
Fig 51. USB Host controller block diagram
BUS
DMA interface
(AHB master)
(AHB slave)
2.2 Architecture
3.1 Pin description
interface
register
Direction
I
I/O
I/O
O
The architecture of the USB host controller is shown below in
The OTG controller has two USB ports indicated by suffixes 1 and 2 in the USB pin names
and referred to as USB port 1 (U1) and USB port 2 (U2) in the following text.
•
•
•
•
OpenHCI specifies the operation and interface of the USB Host Controller and SW
Driver
– USBOperational: Process Lists and generate SOF Tokens.
– USBReset: Forces reset signaling on the bus, SOF disabled.
– USBSuspend: Monitor USB for wakeup activity.
– USBResume: Forces resume signaling on the bus.
The Host Controller has four USB states visible to the SW Driver.
HCCA register points to Interrupt and Isochronous Descriptors List.
ControlHeadED and BulkHeadED registers point to Control and Bulk Descriptors List.
USB HOST BLOCK
INTERFACE
INTERFACE
REGISTER
Description
V
via its corresponding PINSEL register, it is driven
HIGH internally.
Positive differential data
Negative differential data
SoftConnect control signal
GoodLink LED control signal
MASTER
BUS
BUS
status input. When this function is not enabled
Rev. 04 — 26 August 2009
CONTROLLER
HOST
Chapter 14: LPC24XX USB Host controller
port 1
port 2
CONTROL
LOGIC/
PORT
MUX
ATX
Pin category
USB Connector
USB Connector
USB Connector
Control
Control
Figure
14–51.
USB
USB
ATX
ATX
UM10237
© NXP B.V. 2009. All rights reserved.
port
U1
port
U2
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