LPC3250FET296/01,5 NXP Semiconductors, LPC3250FET296/01,5 Datasheet - Page 8

• Manufacturer Part Number: LPC3250FET296/01,5
• Description: IC ARM9 MCU 256K 296-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC32x0r

Specifications of LPC3250FET296/01,5

• Package / Case: 296-TFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 266MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, Motor Control PWM, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: ROMless
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC32
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 256 KB
• Interface Type: EMC
• Maximum Clock Frequency: 266 MHz
• Number Of Timers: 6
• Operating Supply Voltage: 1.31 V to 1.39 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, DK-57TS-LPC3250, DK-57VTS-LPC3250, SOMDIMM-LPC3250
• Development Tools By Supplier: OM11016, OM11021, OM11045
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4962; 935290766551

NXP Semiconductors
ES_LPC3250
Errata sheet
Fig 3.
128 MB DDR SDRAM example
3.3 Ethernet.1: Ethernet TxConsumeIndex register does not update
3.4 DDR.2: DDR EMC_D[15:0] to EMC_DQS[1:0] data output set-up time,
correctly after the first frame is sent
Introduction:
The transmit consume index register defines the descriptor that is going to be transmitted
next by the hardware transmit process. After a frame has been transmitted hardware
increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has
been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is
empty and the transmit channel will stop transmitting until software produces new
descriptors.
Problem:
The TxConsumeIndex register is not updated correctly (from 0 to 1) after the first frame is
sent. After the next frame sent, the TxConsumeIndex register is updated by two (from 0 to
2). This only happens the very first time, so subsequent updates are correct (even those
from 0 to 1, after wrapping the value to 0 once the value of TxDescriptorNumber has been
reached)
Work-around:
Software can correct this situation in many ways; for example, sending a dummy frame
after initialization.
t
Remark: This affects both 1.8 V mobile and 2.5 V DDR SDRAM system implementations.
Introduction:
DDR memory interface signal EMC_DQS[1:0] is source synchronous, defined to be driven
by the MCU center aligned to the data EMC_D[15:0] for writes, while driven by the DDR
memory edge aligned to the EMC_D[15:0] for reads. The basic DDR write timing is shown
in the data sheet Fig 1.
su(Q)
, for MCU write to DDR provides limited timing margin
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 1 February 2011
ES_LPC3250
Errata sheet LPC3250
© NXP B.V. 2011. All rights reserved.
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