LPC2104FBD48/01,15 NXP Semiconductors, LPC2104FBD48/01,15 Datasheet - Page 24
![IC ARM7 MCU FLASH 128K 48-LQFP](/photos/6/64/66484/568-48-lqfp_sot313-2_sml.jpg)
LPC2104FBD48/01,15
Manufacturer Part Number
LPC2104FBD48/01,15
Description
IC ARM7 MCU FLASH 128K 48-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2100r
Datasheet
1.LPC2104FBD480115.pdf
(41 pages)
Specifications of LPC2104FBD48/01,15
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
48-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
60MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC21
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
16 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC2106-PL
Minimum Operating Temperature
- 40 C
Package
48LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4310 - EVAL BOARD LPC2158 W/LCD568-4297 - BOARD EVAL LPC21XX MCB2100622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K568-1756 - BOARD EVAL FOR LPC210X ARM MCU
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4365
935286614151
LPC2104FBD48/01-S
935286614151
LPC2104FBD48/01-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2104FBD48/01,15
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC2104_2105_2106_7
Product data sheet
6.19.1 EmbeddedICE
6.19.2 Embedded trace
6.19 Emulation and debugging
processor clock rate. The second purpose of the APB divider is to allow power savings
when an application does not require any peripherals to run at the full processor rate.
Because the APB divider is connected to the PLL output, the PLL remains active (if it was
running) during Idle mode.
The LPC2104/2105/2106 support emulation and debugging via a JTAG serial port. A trace
port allows tracing program execution. Each of these functions requires a trade-off of
debugging features versus device pins. Because the LPC2104/2105/2106 are provided in
a small package, there is no room for permanently assigned JTAG or Trace pins. An
alternate JTAG port allows an option to debug functions assigned to the pins used by the
primary JTAG port (see
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote
Debug Protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.
The JTAG clock (TCK) must be slower than
interface to operate.
Since the LPC2104/2105/2106 have significant amounts of on-chip memory, it is not
possible to determine how the processor core is operating simply by observing the
external pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability
for deeply embedded processor cores. It outputs information about processor execution to
the trace port.
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
trace port analyzer must capture the trace information under software debugger control.
Instruction trace (or PC trace) shows the flow of execution of the processor and provides a
list of all the instructions that were executed. Instruction trace is significantly compressed
by only broadcasting branch addresses as well as a set of status signals that indicate the
pipeline status on a cycle by cycle basis. Trace information generation can be controlled
by selecting the trigger resource. Trigger resources include address comparators,
counters and sequencers. Since trace information is compressed the software debugger
requires a static image of the code being executed. Self-modifying code cannot be traced
because of this restriction.
Rev. 07 — 20 June 2008
Section
6.8).
1
6
of the CPU clock (CCLK) for the JTAG
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
© NXP B.V. 2008. All rights reserved.
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