Z8F082AQB020SG Zilog, Z8F082AQB020SG Datasheet - Page 145
Z8F082AQB020SG
Manufacturer Part Number
Z8F082AQB020SG
Description
IC ENCORE XP MCU FLASH 8K 8-QFN
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F082AQB020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
6
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
269-3809
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F082AQB020SG
Manufacturer:
Maxim
Quantity:
43
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Low Power Operational Amplifier
Overview
Operation
PS022825-0908
Warning:
The LPO is a general-purpose low power operational amplifier. Each of the three ports of
the amplifier is accessible from the package pins. The LPO contains only one pin configu-
ration: ANA0 is the output/feedback node, ANA1 is the inverting input and ANA2 is the
non-inverting input.
To use the LPO, it must be enabled in the
default state of the LPO is OFF. To use the LPO, the LPO bit must be cleared, turning it
ON
measurements on ANA0 (measurements not involving the LPO output), the LPO bit must
be OFF. Turning the LPO bit ON interferes with normal ADC measurements.
As with other ADC measurements, any pins used for analog purposes must be configured
as such in the GPIO registers (see
page 47).
LPO output measurements are made on ANA0, as selected by the
ADC Control Register
and ANA2 while the amplifier is enabled, which is often useful for determining offset con-
ditions. Differential measurements between ANA0 and ANA2 may be useful for noise
cancellation purposes.
If the LPO output is routed to the ADC, then the
tus Register 1
LPO in an unbuffered mode is not recommended.
When either input is overdriven, the amplifier output saturates at the positive or negative
supply voltage. No instability results.
The LPO bit enables the amplifier even in STOP mode. If the amplifier is not required
in STOP mode, disable it. Failing to perform this results in STOP mode currents
higher than necessary.
(Power Control Register 0 (PWRCTL0)
must also be configured for unity-gain buffered operation. Sampling the
0. It is also possible to make single-ended measurements on ANA1
Port A–D Alternate Function Sub-Registers
Power Control Register 0
on page 35). When making normal ADC
BUFFMODE
Z8 Encore! XP
[2:0] bits of
Low Power Operational Amplifier
Product Specification
ANAIN[3:0]
(PWRCTL0). The
ADC Control/Sta-
®
F082A Series
on
bits of
134
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