Z8F082AQB020SG Zilog, Z8F082AQB020SG Datasheet - Page 41
Z8F082AQB020SG
Manufacturer Part Number
Z8F082AQB020SG
Description
IC ENCORE XP MCU FLASH 8K 8-QFN
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F082AQB020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
6
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
269-3809
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F082AQB020SG
Manufacturer:
Maxim
Quantity:
43
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Low Voltage Detection
Reset Register Definitions
PS022825-0908
Stop Mode Recovery Using the External RESET Pin
Reset Status Register
When the Z8 Encore! XP F082A Series device is in STOP mode and the external RESET
pin is driven Low, a system reset occurs. Because of a glitch filter operating on the RESET
pin, the Low pulse must be greater than the minimum width specified, or it is ignored. See
Electrical Characteristics
In addition to the Voltage Brownout (VBO) Reset described above, it is also possible to
generate an interrupt when the supply voltage drops below a user-selected value. For
details about configuring the Low Voltage Detection (LVD) and the threshold levels avail-
able, see
pin product versions only.
When the supply voltage drops below the LVD threshold, the LVD bit of the Reset Status
(RSTSTAT) register is set to one. This bit remains one until the low-voltage condition
goes away. Reading or writing this bit does not clear it. The LVD circuit can also generate
an interrupt when so enabled, see
is NOT latched, so enabling the interrupt is the only way to guarantee detection of a
transient low voltage event.
The LVD functionality depends on circuitry shared with the VBO block; therefore,
disabling the VBO also disables the LVD.
The following sections define the Reset registers.
The Reset Status (RSTSTAT) register is a read-only register that indicates the source of
the most recent Reset event, indicates a Stop Mode Recovery event, and indicates a
Watchdog Timer time-out. Reading this register resets the upper four bits to 0.
This register shares its address with the Watchdog Timer control register, which is
write-only (see
initiate Stop Mode Recovery without being written to the Port Input Data register or
without initiating an interrupt (if enabled for that pin).
Trim Bit Address 0003H
Table 11
on page 31).
on page 221 for details.
Interrupt Vectors and Priority
on page 159. The LVD function is available on the 8-
Reset, Stop Mode Recovery, and Low Voltage Detection
Z8 Encore! XP
on page 58. The LVD bit
Product Specification
®
F082A Series
30
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