ZLP32300H2832G Zilog, ZLP32300H2832G Datasheet - Page 57

• Manufacturer Part Number: ZLP32300H2832G
• Description: IC CRIMZON Z8 MCU OTP 32K 28SSOP
• Manufacturer: Zilog
• Series: Crimzon™ ZLPr

Specifications of ZLP32300H2832G

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: Brown-out Detect/Reset, HLVD, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 237 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Data Bus Width: 8 bit
• Data Ram Size: 237 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• For Use With: 269-4665 - KIT REMOTE UNVRSL USA 6-FUNCTION
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4507; ZLP32300H2832G

PS020823-0208
Note:
Note:
Table 14. Stop Mode Recovery Source
Any Port 2 bit defined as an output drives the corresponding input to the default state. For
example, if the NOR of P23-P20 is selected as the recovery source and P20 is configured
as an output, the remaining SMR pins (P23-P21) form the NOR equation. This condition
allows the remaining inputs to control the AND/OR function, refer to SMR2 register on
page 54 for other recover sources.
Stop Mode Recovery Delay Select (D5)
This bit, if low, disables the T
tion of this bit is 1. If the ‘fast’ wake up is selected, the Stop Mode Recovery source must
be kept active for at least 10 TpC.
This bit must be set to 1 if a crystal or resonator clock source is used. The T
allows the clock source to stabilize before executing instructions.
Stop Mode Recovery Edge Select (D6)
A 1 in this bit position indicates that a High level on any one of the recovery sources
wakes the Crimzon ZLP32300 from STOP mode. A 0 indicates Low level recovery. The
default is 0 on POR.
Cold or Warm Start (D7)
This bit is read only. It is set to 1 when the device is recovered from STOP mode. The bit
is set to 0 when the device reset is other than Stop Mode Recovery.
SMR:432
D4
0
0
0
0
1
1
1
1
D3
0
0
1
1
0
0
1
1
D2
0
1
0
1
0
1
0
1
Operation
Description of Action
POR and/or external reset recovery
Reserved
P31 transition
P32 transition
P33 transition
P27 transition
Logical NOR of P20 through P23
Logical NOR of P20 through P27
POR
delay after Stop Mode Recovery. The default configura-
Product Specification
Crimzon
Functional Description
®
ZLP32300
POR
delay
53