ST72F262G1M6 STMicroelectronics, ST72F262G1M6 Datasheet - Page 118

MCU 8BIT 4KB FLASH 28-SOIC

ST72F262G1M6

Manufacturer Part Number
ST72F262G1M6
Description
MCU 8BIT 4KB FLASH 28-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72F262G1M6

Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
ST7
No. Of I/o's
22
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
ST72F2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
22
Number Of Timers
4 bit
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7F264-IND/USB, ST72F34X-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Other names
497-5581-5

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
ST72F262G1M6
Manufacturer:
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ST72260Gx, ST72262Gx, ST72264Gx
10-BIT A/D CONVERTER (ADC) (Cont’d)
11.7.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRH register or writing to
any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED A/D clock selection
This bit is set and cleared by software.
Table 22. A/D Clock Selection
1)
setting the ADON bit.
2)
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 4 = SLOW A/D Clock Selection
This bit is set and cleared by software. It works to-
gether with the SPEED bit. Refer to
118/172
EOC SPEED ADON SLOW
The SPEED and SLOW bits must be updated before
Use this setting only if f
7
f
f
CPU
ADC
(See Note 2)
Frequency
f
f
CPU
CPU
/2
/4
CPU
4 MHz
0
SLOW
CH2
(See Note 1)
0
1
0
1
Table
CH1
SPEED
22.
1
1
0
0
CH0
0
Bit 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
DATA REGISTER (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[9:2] MSB of Analog Converted Value
DATA REGISTER (ADCDRL)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Analog Converted Value
D9
7
7
0
D8
0
Channel Pin
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
D7
0
D6
0
D5
0
CH2
0
0
0
0
1
1
D4
0
CH1
0
0
1
1
0
0
D3
D1
CH0
D2
D0
0
1
0
1
0
1
0
0

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