Z16F6411AL20SG Zilog, Z16F6411AL20SG Datasheet - Page 38
Z16F6411AL20SG
Manufacturer Part Number
Z16F6411AL20SG
Description
IC ZNEO MCU FLASH 64K 100LQFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet
1.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F6411AL20SG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
Z16F6x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
4 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
76
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4570
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Bus Widths
PS022008-0810
000080H
000082H
000080H
Figure 8. Alignment of Word and Quad Operations on 16-bit Memories
The ZNEO CPU accesses 8-bit or 16-bit memories. The data buses of the internal
non-volatile memory and internal RAM are 16-bit wide. The internal peripherals are a mix
of 8-bit and 16-bit peripherals. The external memory bus is configured as an 8-bit or 16-bit
memory bus.
If a Word or Quad operation occurs on a 16-bit wide memory, the number of memory
accesses depends on the alignment of the address. If the address is aligned on an even
boundary, a Word operation takes one memory access and a Quad operation takes two
memory accesses. If the address is on an odd boundary (unaligned), a Word operation
takes two memory accesses and a Quad operation takes three memory accesses.
Figure 8
Aligned Word Access
Aligned Quad Access
displays the alignment Word and Quad operations on 16-bit memories.
MSB
MSB
LSB
LSB
000081H
000083H
000081H
P R E L I M I N A R Y
000082H
000080H
000084H
000082H
000080H
Unaligned Word Access
Unaligned Quad Access
LSB
LSB
MSB
MSB
Product Specification
000083H
000081H
000085H
000083H
000081H
ZNEO
Address Space
Z16F Series
23
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