CY8CLED03D02-56LTXI Cypress Semiconductor Corp, CY8CLED03D02-56LTXI Datasheet - Page 10

• Manufacturer Part Number: CY8CLED03D02-56LTXI
• Description: IC POWERPSOC 3CH 1A 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: PowerPSoC® CY8CLEDr

Specifications of CY8CLED03D02-56LTXI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: DALI, DMX512, I²C, IrDA, SPI, UART/USART
• Peripherals: LED, LVD, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-2882 - KIT STARTER POWERPSOC LIGHTING428-2281 - KIT EVAL POWERPSOC LIGHTING428-2271 - KIT EVAL COLOR-LOCK428-2270 - KIT STARTER DEMO LIGHTING770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 428-2925

5. The PSoC Core
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
processor. The CPU uses an interrupt controller with up to 20
vectors to simplify programming of real time embedded events.
The program execution is timed and protected using the included
Sleep and Watchdog Timers (WDT) time and protect program
execution.
Memory encompasses 16K of Flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash uses four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to 4
percent over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. The clocks, together with programmable
clock dividers (as a system resource), provide the flexibility to
integrate almost any timing requirement into the PowerPSoC
device.
PowerPSoC GPIOs provide connection to the CPU, digital, and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
5.1 The Digital System
The digital system contains eight digital PSoC blocks. Each block
is an 8-bit resource that can be used alone or combined with
other blocks to form 8, 16, 24, and 32-bit peripherals, which are
called user module references.
Digital peripheral configurations include those listed below.
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The digital blocks can be connected to any GPIO through a
series of global buses that route any signal to any pin. The buses
also allow signal multiplexing and performing logic operations.
This configurability frees your designs from the constraints of a
fixed peripheral controller.
Document Number: 001-46319 Rev. *E
DALI
DMX512
Counters (8 to 32 bit)
Timers (8 to 32 bit)
UART 8-bit with selectable parity
SPI master and slave
I2C slave and multi-master
Cyclical redundancy checker/generator (8 to 32 bit)
IrDA
Pseudo random sequence generators (8 to 32 bit)
There are four digital blocks in each row. This allows optimum
choice of system resources for your application.
Figure 5-1. Digital System Block Diagram
5.2 The Analog System
The analog system contains six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PowerPSoC analog functions (most
available as user modules) are listed below.
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Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in
Analog-to-digital converters (up to 2, with 6 to 12-bit resolution,
selectable as incremental, Delta Sigma, and SAR)
Filters (2 and 4 pole band-pass, low-pass, and notch)
Amplifiers (up to 2, with selectable gain to 48x)
Instrumentation amplifiers (1 with selectable gain to 93x)
Comparators (up to 2, with 16 selectable thresholds)
DACs (up to 2, with 6 to 9-bit resolution)
Multiplying DACs (up to 2, with 6 to 9-bit resolution)
High current output drivers (two with 30 mA drive as a PSoC
core resource)
1.3V reference (as a system resource)
Modulators
Correlators
Peak detectors
Many other topologies possible
8
8
CY8CLED04G01, CY8CLED03G01
CY8CLED04D01, CY8CLED04D02
CY8CLED03D01, CY8CLED03D02
G IE [7 :0 ]
G IO [7 :0 ]
D B B 0 0
D B 1 0
Figure 5-2
D ig ita l P S o C B lo c k A r r a y
D IG IT A L S Y S T E M
P o rt 2
T o S y s te m B u s
D B B 0 1
D B 1 1
G lo b a l D ig ita l
D B B 0 0
In te rc o n n e c t
R o w 0
P o rt 1
R o w 1
D
on page
D C B 0 2
D B 1 2
P o rt 0
D C B 0 3
D B 1 3
T o A n a lo g
11.
G O O [7 :0 ]
G O E [7 :0 ]
S y s te m
4
4
4
4
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