CY8CLED03D02-56LTXI Cypress Semiconductor Corp, CY8CLED03D02-56LTXI Datasheet - Page 41
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CY8CLED03D02-56LTXI
Manufacturer Part Number
CY8CLED03D02-56LTXI
Description
IC POWERPSOC 3CH 1A 56VQFN
Manufacturer
Cypress Semiconductor Corp
Series
PowerPSoC® CY8CLEDr
Datasheet
1.CY8CLED03D02-56LTXI.pdf
(47 pages)
Specifications of CY8CLED03D02-56LTXI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
DALI, DMX512, I²C, IrDA, SPI, UART/USART
Peripherals
LED, LVD, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
428-2882 - KIT STARTER POWERPSOC LIGHTING428-2281 - KIT EVAL POWERPSOC LIGHTING428-2271 - KIT EVAL COLOR-LOCK428-2270 - KIT STARTER DEMO LIGHTING770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
428-2925
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8CLED03D02-56LTXI
Manufacturer:
Cypress
Quantity:
128
15.17 PSoC Core POR and LVD
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and T
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PowerPSoC Mixed-Signal Array
Technical Reference Manual for more information on the VLT_CR register.
Table 15-31. POR and LVD DC Specifications
Notes
Document Number: 001-46319 Rev. *E
V
V
V
V
V
V
V
V
V
V
V
3. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
4. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
5. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Symbol
PPOR0
PPOR1
PPOR2
LVD0
LVD1
LVD2
LVD3
LVD4
LVD5
LVD6
LVD7
J
≤ 115°C. Typical parameters apply to 5V at 25°C. These are for design guidance only.
VDD Value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VDD Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Description
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
Min
–
–
–
CY8CLED04G01, CY8CLED03G01
CY8CLED04D01, CY8CLED04D02
CY8CLED03D01, CY8CLED03D02
2.36
2.82
4.55
2.45
2.92
3.02
3.13
4.48
4.64
4.73
4.81
Typ
2.51
2.99
Max
2.40
2.95
4.70
3.09
3.20
4.55
4.75
4.83
4.95
[4]
[5]
Units
V
V
V
V
V
V
V
V
V
V
V
VDD must be greater than
or equal to 2.5V during
startup or reset from
Watchdog
Notes
Page 41 of 47
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