C8051F333-GM Silicon Laboratories Inc, C8051F333-GM Datasheet - Page 104
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C8051F333-GM
Manufacturer Part Number
C8051F333-GM
Description
IC 8051 MCU 4KB FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F333-GM
Program Memory Type
FLASH
Program Memory Size
4KB (4K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F330DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1451 - ADAPTER PROGRAM TOOLSTICK F330
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1267
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F333-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
11.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of V
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
The following guidelines are recommended for any system which contains routines which write or erase
Flash from code.
11.4.1. V
11.4.2. PSWE Maintenance
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient
2. Make certain that the minimum V
3. Enable the on-chip V
4. As an added precaution, explicitly enable the V
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas
7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There
8. Minimize the number of variable accesses while PSWE is set to a '1'. Handle pointer address
9. Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has
DD
protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
meet this rise time specification, then add an external V
the device that holds the device in reset until V
drops below 2.7 V.
as possible. This should be the first set of instructions executed after the Reset Vector. For
'C'-based systems, this will involve modifying the startup code added by the 'C' compiler. See
your compiler documentation for more details. Make certain that there are no delays in soft-
ware between enabling the V
Code examples showing this can be found in “AN201: Writing to Flash from Firmware", avail-
able from the Silicon Laboratories web site.
reset source inside the functions that write and erase Flash memory. The V
instructions should be placed just after the instruction to set PSWE to a '1', but before the
Flash write or erase operation instruction.
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exam-
ple, "RSTSRC = 0x02" is correct. "RSTSRC |= 0x02" is incorrect.
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
should be exactly one routine in code that sets PSWE to a '1' to write Flash bytes and one rou-
tine in code that sets PSWE and PSEE both to a '1' to erase Flash pages.
updates and loop variable maintenance outside the "PSWE = 1; ... PSWE = 0;" area. Code
examples showing this can be found in AN201, "Writing to Flash from Firmware", available
from the Silicon Laboratories web site.
been reset to '0'. Any interrupts posted during the Flash write or erase operation will be ser-
Maintenance and the V
DD
, system clock frequency, or temperature. This accidental execution of Flash modi-
DD
monitor and enable the V
DD
DD
monitor
DD
monitor and enabling the V
rise time specification of 1 ms is met. If the system cannot
Rev. 1.7
DD
DD
DD
C8051F330/1/2/3/4/5
monitor and enable the V
reaches 2.7 V and re-asserts RST if V
monitor as a reset source as early in code
DD
brownout circuit to the RST pin of
DD
monitor as a reset source.
DD
DD
monitor enable
monitor as a
107
DD