C8051F333-GM Silicon Laboratories Inc, C8051F333-GM Datasheet - Page 168
![IC 8051 MCU 4KB FLASH 20QFN](/photos/12/15/121597/c8051f333-gm_sml.jpg)
C8051F333-GM
Manufacturer Part Number
C8051F333-GM
Description
IC 8051 MCU 4KB FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F333-GM
Program Memory Type
FLASH
Program Memory Size
4KB (4K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F330DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1451 - ADAPTER PROGRAM TOOLSTICK F330
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1267
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F333-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
- Current page: 168 of 210
- Download datasheet (2Mb)
C8051F330/1/2/3/4/5
172
Bits 7 – 0: SPI0DAT: SPI0 Transmit and Receive Data.
Bits 7 – 0: SCR7 – SCR0: SPI0 Clock Rate.
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
f
SCK
SCR7
f
R/W
Bit7
SCK
R/W
Bit7
=
=
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT
places the data into the transmit buffer and initiates a transfer when in Master Mode. A read
of SPI0DAT returns the contents of the receive buffer.
These bits determine the frequency of the SCK output when the SPI0 module is configured
for master mode operation. The SCK clock frequency is a divided version of the system
clock, and is given in the following equation, where SYSCLK is the system clock frequency
and SPI0CKR is the 8-bit value held in the SPI0CKR register.
for 0 <= SPI0CKR <= 255
200kHz
f
SCK
------------------------- -
2
2000000
SCR6
R/W
Bit6
R/W
Bit6
=
4
+
------------------------------------------------ -
2
SFR Definition 17.3. SPI0CKR: SPI0 Clock Rate
1
SFR Definition 17.4. SPI0DAT: SPI0 Data
SPI0CKR
SCR5
SYSCLK
R/W
Bit5
R/W
Bit5
SCR4
+
R/W
Bit4
R/W
Bit4
1
Rev. 1.7
SCR3
R/W
Bit3
R/W
Bit3
SCR2
R/W
Bit2
R/W
Bit2
SCR1
R/W
Bit1
R/W
Bit1
SFR Address: 0xA3
SFR Address: 0xA2
SCR0
R/W
Bit0
R/W
Bit0
00000000
Reset Value
00000000
Reset Value
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