C8051F300-GM Silicon Laboratories Inc, C8051F300-GM Datasheet - Page 172

• Manufacturer Part Number: C8051F300-GM
• Description: IC 8051 MCU 8K FLASH 11QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F300-GM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 11-VQFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F226DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• No. Of I/o's: 8
• Ram Memory Size: 256Byte
• Cpu Speed: 25MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 11QFN EP
• Device Core: 8051
• Family Name: C8051F30x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1444 - ADAPTER PROGRAM TOOLSTICK F300336-1351 - KIT REF DES TEMP COMPENS RTC336-1348 - KIT STARTER TOOLSTICK336-1283 - KIT REF DESIGN DTMF DECODER336-1278 - KIT TOOL EVAL SYS IN A USB STICK336-1246 - DEV KIT F300/301/302/303/304/305
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1245

C8051F300/1/2/3/4/5
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Revision 2.4 to Revision 2.5
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172
OCUMENT
Removed preliminary tag.
Changed all references of MLP package to QFN package.
Pinout chapter: Figure 4.3: Changed title to “Typical QFN-11 Solder Paste Mask.”
ADC chapter: Added reference to minimum tracking time in the Tracking Modes section.
Comparators chapter: SFR Definition 7.3, CPT0MD: Updated the register reset value and the CP0
response time table.
CIP51 chapter: Updated IDLE mode and recommendations.
CIP51 chapter: Updated Interrupt behavior and EA recommendations.
CIP51 chapter: SFR Defintion 8.4, PSW: Clarified OV flag description.
CIP51 chapter: SFR Defintion 8.8, IP register: Changed “default priority order” to “low priority” for low
priority descriptions.
Reset Sources chapter: Clarified description of VDD Ramp Time.
Reset Sources chapter: Table 9.2, “Reset Electrical Characteristics”: Added VDD Ramp Time and
changed “VDD POR Threshold” to “VDD Monitor Threshold.”
FLASH Memory chapter: Clarified descriptions of FLASH security features.
Oscillators chapter: Table 11.1 “Internal Oscillator Electrical Characteristics”: Added Calibrated Internal
Oscillator specification over a smaller temperature range.
Oscillators chapter: Clarified external crystal initialization steps and added a specific 32.768 kHz crys-
tal example.
Oscillators chapter: Clarified external capacitor example.
SMBus chapter: Figure 14.5, SMB0CF register: Added a description of the behavior of Timer 3 in split
mode if SMBTOE is set.
Timers chapter: Changed references to “TL2” and “TH2” to “TMR2L” and “TMR2H,” respectively.
Fixed variables and applied formatting changes.
Updated Table 1.1 Product Selection Guide to include Lead-free information.
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Rev. 2.6