MC9S08LL8CGT Freescale Semiconductor, MC9S08LL8CGT Datasheet - Page 12

• Manufacturer Part Number: MC9S08LL8CGT
• Description: IC MCU 8BIT 8K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08LL8CGT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 10KB (10K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Processor Series: S08LL
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2080 B
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 31
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: TWR-SER, TWR-ELEV, TWR-S08LL64, TWR-SENSOR-PAK, TWR-S08LL64-KIT, TWR-LCD
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
P
solving
3.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification, ESD stresses were performed for the human body
model (HBM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless instructed otherwise in the device
specification.
12
D
(at equilibrium) for a known T
Equation 3-1
ESD Protection and Latch-Up Immunity
1
Body Model
Latch-up
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
Charge
Model
Human
Device
Model
No.
1
2
3
and
Series resistance
Storage capacitance
Number of pulses per pin
Series resistance
Storage capacitance
Number of pulses per pin
Minimum input voltage limit
Maximum input voltage limit
Human body model (HBM)
Charge device model (CDM)
Latch-up current at T
Equation 3-2
Table 7. ESD and Latch-Up Protection Characteristics
Table 6. ESD and Latch-up Test Conditions
Description
MC9S08LL16 Series MCU Data Sheet, Rev. 6
Rating
A
. Using this value of K, the values of P
iteratively for any value of T
1
A
= 85C
Symbol
Symbol
V
V
I
R1
R1
HBM
CDM
LAT
—
—
C
C
2000
500
100
Min
A
.
Value
1500
–2.5
100
200
7.5
D
3
0
3
and T
Max
—
—
—
J
can be obtained by
Freescale Semiconductor
Unit
Unit
mA
pF
pF


V
V
V
V