C8051F541-IQ Silicon Laboratories Inc, C8051F541-IQ Datasheet - Page 7

• Manufacturer Part Number: C8051F541-IQ
• Description: IC 8051 MCU 16K FLASH 32-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F54xr

Specifications of C8051F541-IQ

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 32-QFP
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 25x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F540DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1672 - BOARD PROTOTYPE W/C8051F540336-1669 - KIT DEVELOPMENT FOR C8051F540
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1674

C8051F54x
Figure 17.3. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 145
Figure 18.1. Port I/O Functional Block Diagram .................................................... 147
Figure 18.2. Port I/O Cell Block Diagram .............................................................. 148
Figure 18.3. Peripheral Availability on Port I/O Pins .............................................. 151
Figure 18.4. Crossbar Priority Decoder in Example Configuration ........................ 152
Figure 19.1. LIN Block Diagram ............................................................................ 170
Figure 20.1. SMBus Block Diagram ...................................................................... 187
Figure 20.2. Typical SMBus Configuration ............................................................ 188
Figure 20.3. SMBus Transaction ........................................................................... 189
Figure 20.4. Typical SMBus SCL Generation ........................................................ 191
Figure 20.5. Typical Master Write Sequence ........................................................ 198
Figure 20.6. Typical Master Read Sequence ........................................................ 199
Figure 20.7. Typical Slave Write Sequence .......................................................... 200
Figure 20.8. Typical Slave Read Sequence .......................................................... 201
Figure 21.1. UART0 Block Diagram ...................................................................... 205
Figure 21.2. UART0 Timing Without Parity or Extra Bit ......................................... 207
Figure 21.3. UART0 Timing With Parity ................................................................ 207
Figure 21.4. UART0 Timing With Extra Bit ............................................................ 207
Figure 21.5. Typical UART Interconnect Diagram ................................................. 208
Figure 21.6. UART Multi-Processor Mode Interconnect Diagram ......................... 209
Figure 22.1. SPI Block Diagram ............................................................................ 214
Figure 22.2. Multiple-Master Mode Connection Diagram ...................................... 217
Figure 22.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
217
Figure 22.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
217
Figure 22.5. Master Mode Data/Clock Timing ....................................................... 219
Figure 22.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 220
Figure 22.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 220
Figure 22.8. SPI Master Timing (CKPHA = 0) ....................................................... 224
Figure 22.9. SPI Master Timing (CKPHA = 1) ....................................................... 224
Figure 22.10. SPI Slave Timing (CKPHA = 0) ....................................................... 225
Figure 22.11. SPI Slave Timing (CKPHA = 1) ....................................................... 225
Figure 23.1. T0 Mode 0 Block Diagram ................................................................. 230
Figure 23.2. T0 Mode 2 Block Diagram ................................................................. 231
Figure 23.3. T0 Mode 3 Block Diagram ................................................................. 232
Figure 23.4. Timer 2 16-Bit Mode Block Diagram ................................................. 237
Figure 23.5. Timer 2 8-Bit Mode Block Diagram ................................................... 238
Figure 23.6. Timer 2 External Oscillator Capture Mode Block Diagram ................ 239
Figure 23.7. Timer 3 16-Bit Mode Block Diagram ................................................. 243
Figure 23.8. Timer 3 8-Bit Mode Block Diagram ................................................... 244
Figure 23.9. Timer 3 External Oscillator Capture Mode Block Diagram ................ 245
Figure 24.1. PCA Block Diagram ........................................................................... 249
Figure 24.2. PCA Counter/Timer Block Diagram ................................................... 251
Rev. 1.1
7