M37544G2AGP#U0 Renesas Electronics America, M37544G2AGP#U0 Datasheet - Page 25

• Manufacturer Part Number: M37544G2AGP#U0
• Description: IC 740 MCU OTP 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37544G2AGP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: QzROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.1.04
REJ03B0012-0104Z
7544 Group
(3) Event counter mode
Timer A counts signals input from the P0
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR
rising or falling by the CNTR
(4) Pulse width HL continuously measurement mode
In the pulse width HL continuously measurement mode, the pulse
width (“H” and “L” levels) input to the P0
CNTR
edges of CNTR
pulse width HL continuously measurement mode is the same as in
period measurement mode.
The count value when trigger input from the CNTR
cepted is retained until Timer A is read once.
Timer A can stop counting by setting “1” to the timer A count stop
bit in any mode.
Also, when Timer A underflows, the timer A interrupt request bit is
set to “1”.
Note on Timer A is described below;
CNTR
CNTR
switch bit.
When this bit is “0”, the CNTR
the falling edge of the CNTR
the CNTR
the CNTR
However, in the pulse width HL continuously measurement mode,
CNTR
edges of CNTR
CNTR
Note on Timer A
1
1
1
1
1
interrupt active edge selection
active edge switch bit.
interrupt active edge depends on the CNTR
interrupt request is generated at both rising and falling
interrupt request is generated at both rising and falling
1
1
pin input signal.
interrupt request bit is set to “1” at the rising edge of
2004.06.08
1
1
pin input signal. Except for this, the operation in
pin input signal regardless of the setting of
1
page 23 of 66
pin input signal can be selected from
1
1
active edge switch bit .
pin input signal. When this bit is “1”,
1
interrupt request bit is set to “1” at
0
0
/CNTR
/CNTR
1
1
pin is measured.
pin.
1
1
active edge
pin is ac-
Fig. 22 Structure of timer A mode register
Fig. 23 Timer count source set register 2
b7
b7
Note : System operates using an on-chip oscillator as a count source
by setting the on-chip oscillator to oscillation enabled by bit 3
of CPUM.
b0
b0
Disable (return “0” when read)
Timer A operating mode bits
b5 b4
CNTR
Timer A count stop bit
0
0
1
1
0 : Count at rising edge in event counter mode
1 : Count at falling edge in event counter mode
0 : Count start
1 : Count stop
Timer count source set register 2
(TCSS2 : address 002F
Timer A mode register
(TAM : address 001D
Timer 1 count source selection bits
Timer A count source selection bits
Disable (return “0” when read)
Measure the falling edge period in period
measurement mode
Falling edge active for CNTR
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR
0 : Timer mode
1 : Period measurement mode
0 : Event counter mode
1 : Pulse width HL continuously
b1 b0
0
0
1
1
b3 b2
0
0
1
1
1
measurement mode
active edge switch bit
0 : f(X
1 : f(X
0 : On-chip oscillator output
1 : Disable
0 : f(X
1 : f(X
0 : On-chip oscillator output
1 : Disable
IN
IN
IN
IN
)/16
)/2
)/16
)/2
16
, initial value: 00
16
, initial value: 00
1
1
interrupt
interrupt
16
)
16
)