R5F21244SNFP#U0 Renesas Electronics America, R5F21244SNFP#U0 Datasheet - Page 392

• Manufacturer Part Number: R5F21244SNFP#U0
• Description: IC R8C MCU FLASH 16K 52LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/24r

Specifications of R5F21244SNFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 17.5
Timer RA Set to timer mode
Timer RA Set the pulse output level from low to start
Timer RA Set the INT1/TRAIO pin to P1_5
Timer RA Set the count source (f1, f2, f8, fOCO)
Timer RA Set the Synch Break width
UART0
UART0
UART0
Hardware LIN Set the LIN operation to stop
Hardware LIN Set to master mode
Hardware LIN Set the LIN operation to start
Hardware LIN Set the register to enable interrupts
Hardware LIN Clear the status flags
Feb 29, 2008
Bits TMOD0 to TMOD2 in TRAMR register ← 000b
TEDGSEL bit in TRAIOC register ← 1
TIOSEL bit in TRAIOC register ← 1
Bits TCK0 to TCK2 in TRAMR register
TRAPRE register
TRA register
Set to transmit/receive mode
(Transfer data length: 8 bits, Internal clock, 1 stop bit,
Parity disabled)
U0MR register
Set the BRG count source (f1, f8, f32)
U0C0CLK0 to 1 bit
Set the bit rate
U0BRG register
Example of Header Field Transmission Flowchart (1)
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in LINCR register
(Bus collision detection, Synch Break detection,
Synch Field measurement)
LINCR register LINE bit ← 0
MST bit in LINCR register ← 1
LINE bit in LINCR register ← 1
Bits B2CLR, B1CLR, B0CLR in LINST register ← 1
Page 373 of 485
A
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
Set the count source and
registers TRA and TRAPRE
as suitable for the Synch
Break period.
Set the BRG count source
and U0BRG register as
appropriate for the bit rate.
During master mode, the
Synch Field measurement-
completed interrupt cannot be
used.
17. Hardware LIN