R5F21276SNFP#U0 Renesas Electronics America, R5F21276SNFP#U0 Datasheet - Page 45
R5F21276SNFP#U0
Manufacturer Part Number
R5F21276SNFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Specifications of R5F21276SNFP#U0
Core Size
16/32-Bit
Program Memory Size
32KB (32K x 8)
Core Processor
R8C
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
No. Of I/o's
25
Ram Memory Size
1.5KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage Range
2.2V To 5.5V
Embedded Interface Type
I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.3 shows the CPU Register Status after
Reset, Figure 5.4 shows the Reset Sequence, and Figure 5.5 shows the OFS Register.
Figure 5.3
Figure 5.4
Table 5.2
P0, P1
P3_1, P3_3 to P3_7
P4_2, P4_5 to P4_7
P5_3, P5_4
Internal reset
signal
Address
(internal address
signal)
CPU clock
RESET pin
fOCO-S
NOTES:
Sep 26, 2008
1. Hardware reset.
2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal
reset signal to “H” at the same.
Pin Name
CPU Register Status after Reset
Reset Sequence
Pin Functions while RESET Pin Level is “L”
10 cycles or more are needed
b15
fOCO-S clock × 32 cycles
IPL
Page 26 of 453
b19
Content of addresses 0FFFEh to 0FFFCh
Start time of flash memory
(CPU clock × 14 cycles)
b15
b15
b15
Input port
Input port
Input port
Input port
(1)
(2)
b8
00000h
U
b7
0000h
0000h
0000h
0000h
I
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Pin Functions
O
CPU clock × 28 cycles
B
S
Z
D
C
b0
b0
b0
b0
b0
0FFFCh
Data register(R0)
Data register(R1)
Data register(R2)
Data register(R3)
Address register(A0)
Address register(A1)
Frame base register(FB)
Interrupt table register(INTB)
Program counter(PC)
User stack pointer(USP)
Interrupt stack pointer(ISP)
Static base register(SB)
Flag register(FLG)
0FFFDh
0FFFEh
Content of reset vector
5. Resets
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