MC9S08GT60CFDE Freescale Semiconductor, MC9S08GT60CFDE Datasheet - Page 201
![IC MCU 60K FLASH 20MHZ 48-QFN](/photos/12/19/121902/mc9s08gt60acfder_sml.jpg)
MC9S08GT60CFDE
Manufacturer Part Number
MC9S08GT60CFDE
Description
IC MCU 60K FLASH 20MHZ 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.M68EVB908GB60E.pdf
(290 pages)
Specifications of MC9S08GT60CFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
For Use With
M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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12.4.4
This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0s.
Writes have no meaning or effect.
SPRF — SPI Read Buffer Full Flag
SPTEF — SPI Transmit Buffer Empty Flag
MODF — Master Mode Fault Flag
Freescale Semiconductor
SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI
data register (SPI1D). SPRF is cleared by reading SPRF while it is set, then reading the SPI data
register.
This bit is set when there is room in the transmit data buffer. It is cleared by reading SPI1S with SPTEF
set, followed by writing a data value to the transmit buffer at SPI1D. SPI1S must be read with
SPTEF = 1 before writing data to SPI1D or the SPI1D write will be ignored. SPTEF generates an
SPTEF CPU interrupt request if the SPTIE bit in the SPI1C1 is also set. SPTEF is automatically set
when a data byte transfers from the transmit buffer into the transmit shift register. For an idle SPI (no
data in the transmit buffer or the shift register and no transfer in progress), data written to SPI1D is
transferred to the shifter almost immediately so SPTEF is set within two bus cycles allowing a second
8-bit data value to be queued into the transmit buffer. After completion of the transfer of the value in
the shift register, the queued value from the transmit buffer will automatically move to the shifter and
SPTEF will be set to indicate there is room for new data in the transmit buffer. If no new data is waiting
in the transmit buffer, SPTEF simply remains set and no data moves from the buffer to the shifter.
MODF is set if the SPI is configured as a master and the slave select input goes low, indicating some
other SPI device is also configured as a master. The SS1 pin acts as a mode fault error input only when
MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by
reading MODF while it is 1, then writing to SPI control register 1 (SPI1C1).
1 = Data available in the receive data buffer.
0 = No data available in the receive data buffer.
1 = SPI transmit buffer empty.
0 = SPI transmit buffer not empty.
1 = Mode fault error detected.
0 = No mode fault error.
SPI Status Register (SPI1S)
Reset:
Read:
Write:
SPRF
Bit 7
0
Figure 12-10. SPI Status Register (SPI1S)
MC9S08GB/GT Data Sheet, Rev. 2.3
= Unimplemented or Reserved
6
0
0
SPTEF
5
1
MODF
4
0
3
0
0
2
0
0
SPI Registers and Control Bits
1
0
0
Bit 0
0
0
201
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