HD64F38024RHV Renesas Electronics America, HD64F38024RHV Datasheet - Page 593
HD64F38024RHV
Manufacturer Part Number
HD64F38024RHV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets
1.US38024-BAG1.pdf
(684 pages)
2.DF36012GFYV.pdf
(1021 pages)
3.DF38102HV.pdf
(145 pages)
Specifications of HD64F38024RHV
Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK38076 - DEV EVAL KIT FOR H8/38076
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F38024RHV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F38024RHV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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TCSRW—Timer Control/Status Register W
Notes: 1. Write is permitted only under certain conditions.
Bit
Initial value
Read/Write
2. 1 on the H8/38124 Group.
Bit 6 Write Inhibit
0
1
Bit 6 is write-enabled
Bit 6 is write-disabled
B6WI
R
7
1
Timer Counter W Write Enable
0
1
8-bit data cannot be written to TCW
8-bit data can be written to TCW
R/(W) *
TCWE
6
0
Bit 4 Write Inhibit
0
1
1
Bit 4 is write-enabled
Bit 4 is write-disabled
B4WI
R
5
1
Timer Control/Status Register W Write Enable
0
1
Data cannot be written to bits 2 and 0
Data can be written to bits 2 and 0
TCSRWE
R/(W) *
Bit 2 Write Inhibit
0
1
4
0
Bit 2 is write-enabled
Bit 2 is write-disabled
Watchdog Timer On
1
0
1
Rev. 8.00 Mar. 09, 2010 Page 571 of 658
Watchdog timer operation is disabled
Clearing conditions:
Reset *
while TCSRWE = 1
Watchdog timer operation is enabled
Setting condition:
0 is written in B2WI and 1 is written in WDON
while TCSRWE = 1
B2WI
Bit 0 Write Inhibit
R
3
1
0
1
2
, or 0 is written in both B2WI and WDON
H'B2
Bit 0 is write-enabled
Bit 0 is write-disabled
Watchdog Timer Reset
Appendix B Internal I/O Registers
0
1
R/(W) *
WDON
Clearing conditions:
Reset by RES pin
When TCSRWE = 1, and 0 is written
in both B0WI and WRST
Setting condition:
When TCW overflows and an internal
reset signal is generated
0 *
2
2
1
BOWI
R
1
1
REJ09B0042-0800
Watchdog Timer
R/(W) *
WRST
0
0
1
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