C8051F005-GQ Silicon Laboratories Inc, C8051F005-GQ Datasheet - Page 118

• Manufacturer Part Number: C8051F005-GQ
• Description: IC 8051 MCU 32K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F00xr

Specifications of C8051F005-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 12-bit
• On-chip Dac: 2-ch x 12-bit
• No. Of I/o's: 32
• Ram Memory Size: 2304Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1188 - DEV KIT FOR F005/006/007
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1187

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
BUSY
Bit7
R
0: SMBus is free
1: SMBus is busy
This bit enables/disables the SMBus serial interface.
0: SMBus disabled.
1: SMBus enabled.
0: No START condition is transmitted.
1: When operating as a master, a START condition is transmitted if the bus is free. (If the
bus is not free, the START is transmitted after a STOP is received.) If STA is set after one
or more bytes have been transmitted or received and before a STOP is received, a repeated
START condition is transmitted. STO should be explicitly cleared before setting STA to
logic 1.
0: No STOP condition is transmitted.
1: Setting STO to logic 1 causes a STOP condition to be transmitted. When a STOP
condition is received, hardware clears STO to logic 0. If both STA and STO are set, a
STOP condition is transmitted followed by a START condition. In slave mode, setting the
STO flag causes SMBus to behave as if a STOP condition was received.
This bit is set by hardware when one of 27 possible SMBus states is entered. (Status code
0xF8 does not cause SI to be set.) When the SI interrupt is enabled, setting this bit causes
the CPU to vector to the SMBus interrupt service routine. This bit is not automatically
cleared by hardware and must be cleared by software.
AA: SMBus Assert Acknowledge Flag.
This bit defines the type of acknowledge returned during the acknowledge cycle on the
SCL line.
0: A “not acknowledge” (high level on SDA) is returned during the acknowledge cycle.
1: An “acknowledge” (low level on SDA) is returned during the acknowledge cycle.
0: No timeout when SCL is high
1: Timeout when SCL high time exceeds limit specified by the SMB0CR value.
0: No timeout when SCL is low.
1: Timeout when SCL low time exceeds limit specified by Timer 3, if enabled.
BUSY: Busy Status Flag.
ENSMB: SMBus Enable.
STA: SMBus Start Flag.
STO: SMBus Stop Flag.
SI: SMBus Serial Interrupt Flag.
FTE: SMBus Free Timer Enable Bit
TOE: SMBus Timeout Enable Bit
ENSMB
R/W
Bit6
Figure 16.4. SMB0CN: SMBus Control Register
STA
R/W
Bit5
STO
R/W
Bit4
Rev. 1.7
R/W
Bit3
SI
R/W
Bit2
AA
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
R/W
FTE
Bit1
(bit addressable)
TOE
R/W
Bit0
0xC0
SFR Address:
Reset Value
00000000
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