MC9S12C128CFAE Freescale Semiconductor, MC9S12C128CFAE Datasheet - Page 224

• Manufacturer Part Number: MC9S12C128CFAE
• Description: IC MCU 16BIT 4K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C128CFAE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 31
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
8.1.2.2
8.1.3
Figure 8-1
224
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•
•
Stop Mode
Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power
standby mode. This aborts any conversion sequence in progress. During recovery from stop mode,
there must be a minimum delay for the stop recovery time, t
conversion sequence.
Wait Mode
Entering wait mode the ATD conversion either continues or aborts for low power depending on the
logical value of the AWAIT bit.
Freeze Mode
In freeze mode the ATD10B8C will behave according to the logical values of the FRZ1 and FRZ0
bits. This is useful for debugging and emulation.
is a block diagram of the ATD.
Block Diagram
MCU Operating Modes
COMPLETE INTERRUPT
CONVERSION
BUS CLOCK
AN7 / PAD7
AN6 / PAD6
AN5 / PAD5
AN4 / PAD4
AN3 / PAD3
AN2 / PAD2
AN1 / PAD1
AN0 / PAD0
V
V
V
V
DDA
SSA
RH
RL
Figure 8-1. ATD10B8C Block Diagram
ATD10B8C
MC9S12C-Family / MC9S12GC-Family
ANALOG
PRESCALER
MUX
CLOCK
APPROXIMATION
REGISTER (SAR)
SUCCESSIVE
Rev 01.24
AND DAC
ATD INPUT ENABLE REGISTER
MODE AND TIMING CONTROL
1
ATD CLOCK
SAMPLE & HOLD
PORT AD DATA REGISTER
SR
RESULTS
, before initiating a new ATD
1
ATD 0
ATD 1
ATD 2
ATD 3
ATD 4
ATD 5
ATD 6
ATD 7
COMPARATOR
+
–
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