HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 220

IC H8/SLP MCU FLASH 80QFP

HD64F38024DV

Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets

Specifications of HD64F38024DV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 8 I/O Ports
Port Data Register 1 (PDR1)
PDR1 is an 8-bit register that stores data for port 1 pins P1
while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states.
If port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
Note: * Pin 1
Port Control Register 1 (PCR1)
PCR1 is an 8-bit register for controlling whether each of the port 1 pins P1
functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in
PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I/O pin.
PCR1 is a write-only register, which is always read as all 1s.
Note: * Pin 1
Rev. 8.00 Mar. 09, 2010 Page 198 of 658
REJ09B0042-0800
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
The register is both readable and writeable.
6
6
and the associated function are not implemented on the H8/38124 Group.
and the associated function are not implemented on the H8/38124 Group.
PCR1
R/W
P1
W
7
0
7
0
7
7
PCR1
P1
R/W
W
6
0
6
0
6
*
6
*
W
5
5
PCR1
R/W
P1
W
0
0
4
4
4
4
7
PCR1
, P1
R/W
P1
W
3
0
3
0
6
3
*, P1
3
4
, and P1
W
2
2
7
, P1
3
. If port 1 is read
6
*, P1
W
1
1
4
, and P1
W
0
0
3

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