HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 405

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7. Relation between RDR reads and bit RDRF
In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when
reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this
indicates that an overrun error has occurred.
When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if bit
RDR is read more than once, the second and subsequent read operations will be performed while
bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to
0, if the read operation coincides with completion of reception of a frame, the next frame of data
may be read. This is illustrated in figure 10.17.
In this case, only a single RDR read operation (not two or more) should be performed after first
checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time
should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is
sufficient margin in an RDR read operation before reception of the next frame is completed. To
be precise in terms of timing, the RDR read should be completed before bit 7 is transferred in
synchronous mode, or before the STOP bit is transferred in asynchronous mode.
Communication
line
RDRF
RDR
Figure 10.17 Relation between RDR Read Timing and Data
Frame 1
Data 1
RDR read
Frame 2
Data 2
Data 1
Section 10 Serial Communication Interface
Rev. 8.00 Mar. 09, 2010 Page 383 of 658
(A)
RDR read
Data 1 is read at point
Data 2 is read at point
(B)
Frame 3
Data 3
Data 2
REJ09B0042-0800
(B)
(A)