MC9S12DB128CPVE Freescale Semiconductor, MC9S12DB128CPVE Datasheet - Page 102

• Manufacturer Part Number: MC9S12DB128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12DB128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.25 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 91
• Eeprom Memory Size: 2048Byte
• Ram Memory Size: 8192Byte
• Cpu Speed: 25MHz
• Rohs Compliant: Yes
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 91
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device User Guide — 9S12DT128DGV2/D V02.15
The total power dissipation can be calculated from:
Two cases with internal voltage regulator enabled and disabled must be considered:
P D
P INT
102
JA
1. Internal Voltage Regulator disabled
2. Internal voltage regulator enabled
Which is the sum of all output currents on I/O ports associated with VDDX and VDDR.
For R
respectively
I
additionally contains the current flowing into the external loads with output high.
Which is the sum of all output currents on I/O ports associated with VDDX and VDDR.
DDR
=
=
=
Total Chip Power Dissipation, [W]
Package Thermal Resistance, [ C/W]
is the current shown in (Table A-7) and not the overall current flowing into VDDR, which
DSON
Chip Internal Power Dissipation, [W]
is valid:
P INT
R DSON
=
I DD V DD
P INT
R DSON
=
P IO
P IO
=
V DD5 V OH
----------------------------------- - for outputs driven high
I DDR V DDR
=
P D
+
=
=
I OH
V OL
----------- - for outputs driven low
I DDPLL V DDPLL
I OL
–
=
i
i
P INT
;
R DSON
R DSON
;
+
+
P IO
I DDA V DDA
I IO
I IO
i
i
2
2
+
I DDA
V DDA
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