M30625FGPGP#U5C Renesas Electronics America, M30625FGPGP#U5C Datasheet - Page 106
M30625FGPGP#U5C
Manufacturer Part Number
M30625FGPGP#U5C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U5C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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LDCTX
[ Syntax ]
[ Function ]
[ Flag Change ]
[ Description Example ]
[ Related Instructions ]
Change
Chapter 3
LDCTX
Flag
• The table data is comprised as shown below.The address indicated by abs20 is the base address of
• This instruction restores task context from the stack area.
• Set the RAM address that contains the task number in abs16 and the start address of table data in abs20.
• The required register information is specified from table data by the task number and the data in the stack area
• Information on transferred registers is configured as shown below. Logic 1 indicates a register to be
LDCTX
abs20
the table. The data stored at an address apart from the base address as much as twice the content of
abs16 indicates register information, and the next address contains the stack pointer correction value.
is transferred to each register according to the specified register information. Then the SP correction value is
added to the stack pointer (SP). For this SP correction value, set the number of bytes you want to the trans-
ferred.
transferred and logic 0 indicates a register that is not transferred.
U
I
D i r e c t i o n i n
which address
increases
abs16,abs20
Base address
of table
Ram,Rom_TBL
Functions
O
B
S
STCTX
*1
Z
Register information for the task whose task number = n
SP correction value for the task whose task number = n
Register information for the task whose task number = 0. (See the above diagram.)
Register information for the task whose task number = 1. (See the above diagram.)
SP correction value for the task whose task number = 0. (See the above diagram.)
SP correction value for the task whose task number = 1. (See the above diagram.)
MSB
D
FB SB A1 A0 R3 R2 R1 R0
n=0 to 255
C
Transferred sequentially
beginning with R0
LoaD ConTeXt
Restore context
88
[ Instruction Code/Number of Cycles ]
LSB
*1
*1
. (See the above diagram.)
. (See the above diagram.)
LDCTX
3.2 Functions
Page= 192
abs16 2
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