M30625FGPGP#U5C Renesas Electronics America, M30625FGPGP#U5C Datasheet - Page 273
M30625FGPGP#U5C
Manufacturer Part Number
M30625FGPGP#U5C
Description
IC M16C MCU FLASH 256K 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U5C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Chapter 5
Figure 5.3.1. Interrupt response time
Table 5.3.1 Interrupt Sequence Execution Time
*1 Add two cycles for the DBC interrupt. Add one cycle for the address match and single-step interrupts.
*2 Allocate interrupt vector addresses in even addresses as must as possible.
Interrupt vector address
5.3.1 Interrupt Response Time
(a) Time from when interrupt request is generated to when the instruction then under execution is completed
(b) Time in which the interrupt sequence is executed
The interrupt response time means a period of time from when an interrupt request is generated till when
the first instruction of the interrupt routine is executed. This period consists of time (a) from when an
interrupt request is generated to when the instruction then under way is completed and time (b) in which
an interrupt sequence is executed. Figure 5.3.1 shows the interrupt response time.
Time (a) varies with each instruction being executed. The DIVX instruction requires a maximum time
that consists of 30 cycles (without wait state) .
Time (b) is shown below.
Interrupt request generated
Odd address
Odd address
Even address
Even address
Interrupt
*2
*2
________
Instruction
Stack pointer (SP) value
Interrupt response time
(a)
Even address
Even address
Odd address
Odd address
Interrupt request acknowledged
Interrupt sequence
(b)
255
Without wait state
16 bits data bus
18 cycle
19 cycle
19 cycle
20 cycle
Instruction in interrupt
routine
*1
*1
*1
*1
Without wait state
5.3 Interrupt Sequence
8 bits data bus
Time
20 cycle
20 cycle
20 cycle
20 cycle
*1
*1
*1
*1
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