M30626FHPGP#U3C Renesas Electronics America, M30626FHPGP#U3C Datasheet - Page 231
![IC M16C MCU FLASH 384K 100LQFP](/photos/12/21/122189/m30626fhpgp_u3c_sml.jpg)
M30626FHPGP#U3C
Manufacturer Part Number
M30626FHPGP#U3C
Description
IC M16C MCU FLASH 384K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30626FHPGP#U3C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
17.1.3.8
If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial interface
operates as described below.
Note that when UARTi transmission/reception is started using this function, the TI does not change state. Note
also that when using this function, the selected transfer clock should be an external clock.
•
•
•
Jan 10, 2006
The transmit shift register is initialized, and the content of the UiTB register is transferred to the transmit
shift register. In this way, the serial interface starts sending data synchronously with the next clock pulse
applied. However, the UARTi output value does not change state and remains the same as when a start
condition was detected until the first bit of data is output synchronously with the input clock.
The receive shift register is initialized, and the serial interface starts receiving data synchronously with the
next clock pulse applied.
The SWC bit is set to “1” (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the
falling edge of the 9th clock pulse.
Initialization of Transmission/Reception
Page 214 of 390
17. Serial Interface
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