AT90USB162-16MUR Atmel, AT90USB162-16MUR Datasheet - Page 235

• Manufacturer Part Number: AT90USB162-16MUR
• Description: IC AVR MCU 16K FLASH 32QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB162-16MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, PS/2, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFN
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART, debugWIRE
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: AT90USB162-16MURTR; AT90USB162-16MUTR; AT90USB162-16MUTR

23.7.5
23.7.6
23.7.7
23.7.8
23.7.9
7707F–AVR–11/10
Consideration While Updating BLS
Prevent Reading the RWW Section During Self-Programming
Setting the Boot Loader Lock Bits by SPM
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is
blocked for reading. How to move the interrupts is described in
Special care must be taken if the user allows the Boot Loader section to be updated by leaving
Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the
entire Boot Loader, and further software updates might be impossible. If it is not necessary to
change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to
protect the Boot Loader software from any internal software changes.
During Self-Programming (either Page Erase or Page Write), the RWW section is always
blocked for reading. The user software itself must prevent that this section is addressed during
the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW
section is busy. During Self-Programming the Interrupt Vector table should be moved to the BLS
as described in
the RWW section after the programming is completed, the user software must clear the
RWWSB by writing the RWWSRE. See
page 237
To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR
and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits
are the Boot Lock bits that may prevent the Application and Boot Loader section from any soft-
ware update by the MCU.
See
Flash access.
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR.
The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to
load the Z-pointer with 0x0001 (same as used for reading the lO
is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits. When pro-
gramming the Lock bits the entire Flash can be read during the operation.
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an (E)LPM
instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in
SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET and
SPMEN bits will auto-clear upon completion of reading the Lock bits or if no (E)LPM instruction
Bit
R0
Table 23-2
for an example.
7
1
“Interrupts” on page
and
Table 23-3
6
1
for how the different settings of the Boot Loader bits affect the
5
BLB12
63, or the interrupts must be disabled. Before addressing
“Simple Assembly Code Example for a Boot Loader” on
4
BLB11
3
BLB02
2
BLB01
“Interrupts” on page
ck
AT90USB82/162
bits). For future compatibility it
1
1
0
1
63.
235