SAK-XC2786X-96F66L AC Infineon Technologies, SAK-XC2786X-96F66L AC Datasheet - Page 43
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SAK-XC2786X-96F66L AC
Manufacturer Part Number
SAK-XC2786X-96F66L AC
Description
IC MCU 16BIT FLASH PG-LQFP-144
Manufacturer
Infineon Technologies
Series
XC27x6Xr
Datasheet
1.SAK-XC2786X-96F66L_AC.pdf
(120 pages)
Specifications of SAK-XC2786X-96F66L AC
Core Processor
C166SV2
Core Size
16/32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
I²S, POR, PWM, WDT
Number Of I /o
116
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
51K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
KX2786X96F66LACXT
SAK-XC2786X-96F66LACINTR
SP000369364
SAK-XC2786X-96F66LACINTR
SP000369364
3.4
With a minimum interrupt response time of 7/11
program execution), the XC2786X can react quickly to the occurrence of non-
deterministic events.
The architecture of the XC2786X supports several mechanisms for fast and flexible
response to service requests; these can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to be
serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
Where in a standard interrupt service the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the
current CPU activity to perform a PEC service. A PEC service implies a single byte or
word data transfer between any two memory locations with an additional increment of
either the PEC source pointer, the destination pointer, or both. An individual PEC
transfer counter is implicitly decremented for each PEC service except when performing
in the continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source-related vector location. PEC services are
particularly well suited to supporting the transmission or reception of blocks of data. The
XC2786X has eight PEC channels, each whith fast interrupt-driven data transfer
capabilities.
Each of the possible interrupt nodes has a separate control register containing an
interrupt request flag, an interrupt enable flag and an interrupt priority bitfield. Each node
can be programmed by its related register to one of sixteen interrupt priority levels. Once
accepted by the CPU, an interrupt service can only be interrupted by a higher-priority
service request. For standard interrupt processing, each possible interrupt node has a
dedicated vector location.
Fast external interrupt inputs can service external interrupts with high-precision
requirements. These fast interrupt inputs feature programmable edge detection (rising
edge, falling edge, or both edges).
Software interrupts are supported by the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
Table 6
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not assigned to peripherals (unassigned nodes) may be
1) Depending if the jump cache is used or not.
Data Sheet
used to generate software-controlled interrupt requests by setting the respective
interrupt request bit (xIR).
shows all of the possible XC2786X interrupt sources and the corresponding
Interrupt System
41
1)
CPU clocks (in the case of internal
XC2000 Family Derivatives
Functional Description
V2.1, 2008-08
XC2786X