SAK-C164CI-8E25M DB Infineon Technologies, SAK-C164CI-8E25M DB Datasheet - Page 55
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SAK-C164CI-8E25M DB
Manufacturer Part Number
SAK-C164CI-8E25M DB
Description
IC MCU 16BIT 64KB OTP MQFP-80-1
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C164CI-8EM_CB.pdf
(79 pages)
Specifications of SAK-C164CI-8E25M DB
Core Processor
C166
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
59
Program Memory Size
64KB (64K x 8)
Program Memory Type
OTP
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-SQFP
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
ASC, CAN, SSC
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
59
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Packages
PG-MQFP-80
Max Clock Frequency
25.0 MHz
Sram (incl. Cache)
4.0 KByte
Can Nodes
1
A / D Input Lines (incl. Fadc)
8
Program Memory
64.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
K164CI8E25MDBNP
K164CI8E25MDBXP
SAK-C164CI-8E25MDB
SAK-C164CI-8E25MDB
SAK-C164CI-8E25MDBIN
SAKC164CI8E25MDBX
SP000104057
K164CI8E25MDBXP
SAK-C164CI-8E25MDB
SAK-C164CI-8E25MDB
SAK-C164CI-8E25MDBIN
SAKC164CI8E25MDBX
SP000104057
P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register
RSTCON under software control.
Table 11
generation mode.
Table 11
CLKCFG
(RP0H.7-5)
1)
2)
3)
Prescaler Operation
When prescaler operation is configured (CLKCFG = 001
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
the duration of an individual TCL) is defined by the period of the input clock
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.
f
clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.
Data Sheet
CPU
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
Please note that pin P0.15 (corresponding to RP0H.7) is inverted in emulation mode, and thus also in EHM.
The external clock input range refers to a CPU clock range of 10 … 25 MHz.
The maximum frequency depends on the duty cycle of the external clock signal.
=
f
OSC
1)
associates the combinations of these three bits with the respective clock
× F). With every F’th transition of
CPU Frequency
f
f
f
f
f
f
f
f
f
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
C164CI Clock Generation Modes
CPU
f
CPU
=
× 4
× 3
× 2
× 5
× 1
× 1.5
/ 2
× 2.5
f
OSC
is half the frequency of
× F
f
OSC
External Clock
Input Range
2.5 to 6.25 MHz
3.33 to 8.33 MHz
5 to 12.5 MHz
2 to 5 MHz
1 to 25 MHz
6.66 to 16.66 MHz
2 to 50 MHz
4 to 10 MHz
for any TCL.
51
f
f
Table
OSC
OSC
2)
the PLL circuit synchronizes the CPU
and the high and low time of
11). The PLL multiplies the input
Notes
Default configuration
–
–
–
Direct drive
–
CPU clock via prescaler
–
B
) the CPU clock is derived from
3)
C164CL/SL
V2.0, 2001-05
C164CI/SI
f
OSC
f
CPU
.
(i.e.