SAK-C164CI-8E25M DB Infineon Technologies, SAK-C164CI-8E25M DB Datasheet - Page 70

• Manufacturer Part Number: SAK-C164CI-8E25M DB
• Description: IC MCU 16BIT 64KB OTP MQFP-80-1
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C164CI-8E25M DB

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: OTP
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-SQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: ASC, CAN, SSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Packages: PG-MQFP-80
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 4.0 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 8
• Program Memory: 64.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: K164CI8E25MDBNP; K164CI8E25MDBXP; SAK-C164CI-8E25MDB; SAK-C164CI-8E25MDB; SAK-C164CI-8E25MDBIN; SAKC164CI8E25MDBX; SP000104057

Demultiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
Parameter
Data valid to WR
Data hold after WR
ALE rising edge after RD,
WR
Address hold after WR
ALE falling edge to CS
CS low to Valid Data In
CS hold after RD, WR
ALE falling edge to RdCS,
WrCS (with RW-delay)
ALE falling edge to RdCS,
WrCS (no RW-delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
(with RW-delay)
Data Sheet
1)
3)
2)
3)
3)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
22
24
26
28
38
39
41
42
43
46
47
48
49
50
51
53
A
+
CC 20 +
CC 10 +
CC -10 +
CC 0 +
CC -4 -
CC 6 +
CC 16 +
CC -4 +
CC 30 +
CC 50 +
CC 26 +
SR –
SR –
SR –
SR 0
SR –
t
C
+
t
min.
F
Max. CPU Clock
(80 ns at 25 MHz CPU clock without waitstates)
t
t
t
F
F
t
= 25 MHz
A
t
t
t
t
t
t
A
66
C
F
A
C
C
C
t
F
max.
–
–
–
–
10 -
40 +
t
–
–
–
16 +
36 +
–
–
–
–
20 +
C
+ 2
t
t
t
t
A
t
C
C
F
A
1 / 2TCL = 1 to 25 MHz
min.
2TCL - 20
+
TCL - 10
+
-10 +
0 +
-4 -
–
TCL - 14
+
TCL - 4
+
-4
+
–
–
2TCL - 10
+
3TCL - 10
+
2TCL - 14
+
0
–
Variable CPU Clock
t
t
t
t
t
t
t
t
C
F
F
A
A
C
C
C
t
t
F
A
t
F
max.
–
–
–
–
10 -
3TCL - 20
+
–
–
–
2TCL - 24
+
3TCL - 24
+
–
–
–
–
2TCL - 20
+ 2
t
t
t
C
C
C
t
A
C164CL/SL
t
+ 2
V2.0, 2001-05
A
+
C164CI/SI
t
t
F
A
1)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns