PIC12F675-I/MF Microchip Technology, PIC12F675-I/MF Datasheet - Page 52

• Manufacturer Part Number: PIC12F675-I/MF
• Description: IC MCU CMOS 1K FLASH W/AD 8-DFN
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F675-I/MF

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232, USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 53270-913
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFNAC164032 - ADAPTER PICSTART PLUS 8DFN/DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC12F629/675
8.7
Data memory can be code protected by programming
the CPD bit to ‘0’.
When the data memory is code protected, the CPU is
able to read and write data to the data EEPROM. It is
recommended to code protect the program memory
when code protecting data memory. This prevents
anyone from programming zeroes over the existing
code (which will execute as NOPs) to reach an added
routine, programmed in unused program memory,
which
Programming unused locations to ‘0’ will also help
prevent data memory code protection from becoming
breached.
TABLE 8-1:
DS41190G-page 52
0Ch
9Ah
9Bh
9Ch
9Dh
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘
Note 1: EECON2 is not a physical register.
Address
outputs
Data EEPROM Operation During
Code Protect
Shaded cells are not used by data EEPROM module.
PIR1
EEDATA
EEADR
EECON1
EECON2
Name
the
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
(1)
contents
EEPROM Control Register 2
EEPROM Data Register
EEIF
Bit 7
—
—
EEPROM Address Register
ADIF
of
Bit 6
—
data
Bit 5
—
—
memory.
Bit 4
—
—
WRERR WREN
CMIF
Bit 3
0
’, q = value depends upon condition.
Bit 2
—
Bit 1
WR
—
TMR1IF 00-- 0--0 00-- 0--0
Bit 0
 2010 Microchip Technology Inc.
RD
0000 0000 0000 0000
-000 0000 -000 0000
---- x000 ---- q000
---- ---- ---- ----
POR, BOD
Value on
Value on all
Resets
other