PIC32MX340F128H-80I/MR Microchip Technology, PIC32MX340F128H-80I/MR Datasheet - Page 39

• Manufacturer Part Number: PIC32MX340F128H-80I/MR
• Description: IC MCU 32BIT 128KB FLASH 64QFN
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX340F128H-80I/MR

• Core Size: 32-Bit
• Program Memory Size: 128KB (128K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Controller Family/series: PIC32
• No. Of I/o's: 53
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 5
• Embedded Interface Type: EUSART, I2C, PSP, SPI
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EUART, I2C, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.3
The PIC32MX3XX/4XX Family core offers a number of
power management features, including low-power
design, active power management and power-down
modes of operation. The core is a static design that
supports slowing or halting the clocks, which reduces
system power consumption during idle periods.
3.3.1
The mechanism for invoking power-down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 25.0
“Power-Saving Features”.
3.3.2
The majority of the power consumed by the
PIC32MX3XX/4XX Family core is in the clock tree and
clocking registers. The PIC32MX family uses extensive
use of local gated-clocks to reduce this dynamic power
consumption.
© 2010 Microchip Technology Inc.
Power Management
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
LOCAL CLOCK GATING
3.4
The PIC32MX3XX/4XX Family core provides for an
Enhanced JTAG (EJTAG) interface for use in the
software debug of application and kernel code. In
addition to standard user mode and kernel modes of
operation, the PIC32MX3XX/4XX Family core provides
a Debug mode that is entered after a debug exception
(derived from a hardware breakpoint, single-step
exception, etc.) is taken and continues until a debug
exception return (DERET) instruction is executed.
During this time, the processor executes the debug
exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for
transferring
PIC32MX3XX/4XX Family core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification define what
registers are selected and how they are used.
PIC32MX3XX/4XX
EJTAG Debug Support
test
data
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DS61143G-page 39
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