PIC16LC77-04I/L Microchip Technology, PIC16LC77-04I/L Datasheet - Page 133
![IC MCU OTP 8KX14 A/D PWM 44PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC16LC77-04I/L
Manufacturer Part Number
PIC16LC77-04I/L
Description
IC MCU OTP 8KX14 A/D PWM 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC77-04I/L
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
14KB (8K x 14)
Program Memory Type
OTP
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 6 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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14.3
The PIC16CXX differentiates between various kinds of
reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (normal operation)
• Brown-out Reset (BOR) (PIC16C72/73A/74A/76/
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR reset during SLEEP, and Brown-
out Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared differ-
ently in different reset situations as indicated in
Table 14-5 and Table 14-6. These bits are used in soft-
ware to determine the nature of the reset. See
Table 14-8 for a full description of reset states of all reg-
isters.
FIGURE 14-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1997 Microchip Technology Inc.
77)
MCLR
OSC1
V
DD
2: Brown-out Reset is implemented on the PIC16C72/73A/74A/76/77.
3: See Table 14-3 and Table 14-4 for time-out situations.
Reset
Applicable Devices
72 73 73A 74 74A 76 77
On-chip
RC OSC
OST/PWRT
Brown-out
V
(1)
Module
detect
WDT
DD
Reset
rise
OST
PWRT
(2)
10-bit Ripple counter
Reset
WDT
10-bit Ripple counter
Time-out
BODEN
Power-on Reset
External
Reset
SLEEP
Enable PWRT
Enable OST
A simplified block diagram of the on-chip reset circuit is
shown in Figure 14-8.
The PIC16C72/73A/74A/76/77 have a MCLR noise fil-
ter in the MCLR reset path. The filter will detect and
ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
(3)
PIC16C7X
S
R
DS30390E-page 133
Q
Chip_Reset
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