PIC16LC77-04I/L Microchip Technology, PIC16LC77-04I/L Datasheet - Page 91
![IC MCU OTP 8KX14 A/D PWM 44PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC16LC77-04I/L
Manufacturer Part Number
PIC16LC77-04I/L
Description
IC MCU OTP 8KX14 A/D PWM 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC77-04I/L
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
14KB (8K x 14)
Program Memory Type
OTP
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 6 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Figure 11-19 and Figure 11-20 show Master-transmit-
ter and Master-receiver data transfer sequences.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START con-
dition (Sr) must be generated. This condition is identi-
cal to the start condition (SDA goes high-to-low while
FIGURE 11-19: MASTER-TRANSMITTER SEQUENCE
FIGURE 11-20: MASTER-RECEIVER SEQUENCE
FIGURE 11-21: COMBINED FORMAT
Transfer direction of data and acknowledgment bits depends on R/W bits.
Sr
A master reads a slave immediately after the first byte.
Combined format - A master addresses a slave with a 10-bit address, then transmits
1997 Microchip Technology Inc.
For 7-bit address:
Combined format:
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
S
S
For 7-bit address:
Slave Address
S
From slave to master
From master to slave
Slave Address R/W A Data A Data A P
Slave Address R/W A Data A/A Sr
From slave to master
From master to slave
First 7 bits
Slave Address R/W A Data A Data A/A P
From slave to master
From master to slave
'1' (read)
'0' (write)
(write)
(read)
R/W A
data to this slave and reads data from this slave.
(n bytes - acknowledge)
(n bytes - acknowledge)
Slave Address
Second byte
data transferred
data transferred
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Sr = repeated
Start Condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(n bytes + acknowledge)
(read or write)
Slave Address R/W A Data A/A
A
72 73 73A 74 74A 76 77
Data
Applicable Devices
A
(write)
Data A/A
For 10-bit address:
S
SCL is high), but occurs after a data transfer acknowl-
edge pulse (not the bus-free state). This allows a mas-
ter to send “commands” to the slave and then receive
the requested information or to address a different
slave device. This sequence is shown in Figure 11-21.
For 10-bit address:
S
Slave Address
Direction of transfer
may change at this point
Slave Address
First 7 bits
A master transmitter addresses a slave receiver
with a 10-bit address.
First 7 bits
Sr Slave Address
A master transmitter addresses a slave receiver
with a 10-bit address.
Sr
Slave Address
(write)
Data A
First 7 bits
First 7 bits
(write)
P
R/W A1 Slave Address
R/W A1 Slave Address
(read)
(read)
Data
R/W A Data A
R/W A3
Second byte
Second byte
A/A
PIC16C7X
P
Data A
DS30390E-page 91
A2
A2
Data
Data
A
A P
P
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