PIC18F4439-I/P Microchip Technology, PIC18F4439-I/P Datasheet - Page 23
![IC MCU FLASH 6KX16 EE A/D 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4439-I/P
Manufacturer Part Number
PIC18F4439-I/P
Description
IC MCU FLASH 6KX16 EE A/D 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2439-ISO.pdf
(322 pages)
3.PIC18F2439-ISO.pdf
(6 pages)
4.PIC18F2439-ISO.pdf
(34 pages)
Specifications of PIC18F4439-I/P
Core Size
8-Bit
Program Memory Size
12KB (6K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
640 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
32
Eeprom Memory Size
256Byte
Ram Memory Size
640Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
640 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4439-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2439-ISO PDF datasheet #2
- PIC18F2439-ISO PDF datasheet #3
- PIC18F2439-ISO PDF datasheet #4
- Current page: 23 of 322
- Download datasheet (7Mb)
FIGURE 2-5:
2.5
When the device executes a SLEEP instruction, the
oscillator is turned off and the device is held at the
beginning of an instruction cycle (Q1 state). With the
oscillator off, the OSC1 and OSC2 signals will stop
oscillating. Since all the transistor switching currents
have been removed, SLEEP mode achieves the lowest
current consumption of the device (only leakage cur-
rents). Enabling any on-chip feature that will operate
during SLEEP will increase the current consumed dur-
ing SLEEP. The user can wake from SLEEP through
external RESET, Watchdog Timer Reset, or through an
interrupt.
2.6
Power-up delays are controlled by two timers, so that
no external RESET circuitry is required for most appli-
cations. The delays ensure that the device is kept in
RESET, until the device power supply and clock are
stable. For additional information on RESET operation,
see Section 3.0.
TABLE 2-2:
2002 Microchip Technology Inc.
ECIO
EC
HS
Note:
OSC Mode
(from Configuration
Effects of SLEEP Mode on the
On-Chip Oscillator
Power-up Delays
bit Register)
See Table 3-1 in the “Reset” section, for time-outs due to SLEEP and MCLR Reset.
OSC1
OSC2
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Feedback inverter disabled, at quiescent
PLL BLOCK DIAGRAM
PLL Enable
Crystal
Osc
HS Osc
voltage level
OSC1 Pin
Floating
Floating
F
F
IN
OUT
Comparator
Phase
Preliminary
Loop
Filter
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.
With the PLL enabled (HS/PLL Oscillator mode), the
time-out sequence following a Power-on Reset is differ-
ent from other Oscillator modes. The time-out
sequence is as follows:
1.
2.
3.
÷
4
The PWRT time-out is invoked after a POR time
delay has expired.
The Oscillator Start-up Timer (OST) is invoked.
However, this is still not a sufficient amount of
time to allow the PLL to lock at high frequencies.
The PWRT timer is used to provide an additional
fixed 2 ms (nominal) time-out to allow the PLL
ample time to lock to the incoming clock
frequency.
Feedback inverter disabled, at quiescent
Configured as PORTA, bit 6
VCO
PIC18FXX39
voltage level
At logic low
OSC2 Pin
DS30485A-page 21
SYSCLK
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