PIC18F4439-I/P Microchip Technology, PIC18F4439-I/P Datasheet - Page 308
![IC MCU FLASH 6KX16 EE A/D 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4439-I/P
Manufacturer Part Number
PIC18F4439-I/P
Description
IC MCU FLASH 6KX16 EE A/D 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2439-ISO.pdf
(322 pages)
3.PIC18F2439-ISO.pdf
(6 pages)
4.PIC18F2439-ISO.pdf
(34 pages)
Specifications of PIC18F4439-I/P
Core Size
8-Bit
Program Memory Size
12KB (6K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
640 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
32
Eeprom Memory Size
256Byte
Ram Memory Size
640Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
640 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4439-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2439-ISO PDF datasheet #2
- PIC18F2439-ISO PDF datasheet #3
- PIC18F2439-ISO PDF datasheet #4
- Current page: 308 of 322
- Download datasheet (7Mb)
PIC18FXX39
APPENDIX C:
The considerations for converting applications from
previous versions of PIC18 microcontrollers (i.e.,
PIC18FXX2 devices) are listed in Table C-1.
A specific list of resources that are unavailable to
PIC18FXX2 applications in PIC18FXX39 devices is
presented in Table C-2.
TABLE C-1:
TABLE C-2:
DS30485A-page 306
Pins
Available Packages
Voltage Range
Frequency Range
Available Program Memory (bytes)
Available Data RAM (bytes)
Data EEPROM
Interrupt Sources
Interrupt Priority Levels
Timers (available to users)
Timer1 Oscillator option
Oscillator Switching
Capture/Compare/PWM
Motor Control Kernel
A/D
Communications
Code Protection
I/O Resources
Registers
SFR bits
Interrupts and
Interrupt Resources
Timer Resources
CCP Resources
Configuration Word bits
Resource Type
Characteristic
CONVERSION CONSIDERATIONS BETWEEN PIC18FXX2 AND PIC18FXX39 DEVICES
UNAVAILABLE RESOURCES (COMPARED TO PIC18FXX2)
CONVERSION
CONSIDERATIONS
RC1; RC2; T1OSO; T1OSI
OSCEN; CCP2MX; CP3; WRT3; EBTR3
CCP1CON; CCP2CON; CCPR1L; CCPR2L; TMR2; PR2; T2CON; OSCCON
CCP1IE; CCP1IF; CCP1IP; CCP21E; CCP21F; CCP2IP; T1OSCEN; T3CCP1; TMR2ON;
TOUTPS<3:0>; T2CKPS<1:0>; T3CCP2; SFS; RC1; RC2; TRISC1; TRISC2; LATC1; LATC2
CCP1 Capture/Compare match; CCP2 Capture/Compare match; High priority interrupts
(when Motor Control is used; reserved for Timer2)
Timer2 (available only through the Motor Control kernel); Timer2 as a clock source for
MSSP module (SPI mode)
Capture and Compare functionality; Timer1 reset on special event; Timer3 reset on special
event; A/D conversion on special event; Interrupt on special event
DIP, PDIP, SOIC, PLCC, QFN, TQFP
PSP, AUSART, MSSP (SPI and I
By 8K block with separate 512-byte
boot block; protection from external
reads and writes, Table Read and
high priority (vector at 0018h)
low priority (vector at 0008h)
7 conversion clock selects
10-bit, 5 or 8 channels,
intra-block Table Read
DC - 40 MHz
Preliminary
PIC18FXX2
768 or 1536
16K or 32K
Two levels:
2.0 - 5.5V
28/40/44
17 or 18
2 CCP
256
yes
yes
no
4
Item(s)
2
C)
block Table Read; Block 3 not protected
reads and writes, Table Read and intra-
One level when using Motor Control:
PSP, AUSART, MSSP (SPI and I
By 8K block with separate 512-byte
2 PWM only, available only through
boot block; protection from external
DIP, PDIP, SOIC, QFN, TQFP
4 - 40 MHz (20 MHz optimal)
7 conversion clock selects
10-bit, 5 or 8 channels,
2002 Microchip Technology Inc.
Motor Control kernel
on PIC18FX539
vector at 0008h
PIC18FXX39
640 or 1408
12K or 24K
2.0 - 5.5V
28/40/44
15 or 16
256
yes
no
no
3
2
C)
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