DSPIC33FJ128MC706-I/PT Microchip Technology, DSPIC33FJ128MC706-I/PT Datasheet - Page 262
![IC DSPIC MCU/DSP 128K 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
DSPIC33FJ128MC706-I/PT
Manufacturer Part Number
DSPIC33FJ128MC706-I/PT
Description
IC DSPIC MCU/DSP 128K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
3.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
4.DSPIC33FJ128GP706-IPT.pdf
(371 pages)
Specifications of DSPIC33FJ128MC706-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
64-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
16 KB
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Data Rom Size
4096 B
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128MC706-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ12GP201-ISO PDF datasheet
- DSPIC33FJ64MC506-IPT PDF datasheet #2
- DSPIC33FJ64MC506-IPT PDF datasheet #3
- DSPIC33FJ128GP706-IPT PDF datasheet #4
- Current page: 262 of 340
- Download datasheet (5Mb)
dsPIC33FJXXXMCX06/X08/X10
23.5
dsPIC33FJXXXMCX06/X08/X10 devices implement a
JTAG interface, which supports boundary scan device
testing, as well as in-circuit programming. Detailed
information on the interface will be provided in future
revisions of the document.
23.6
The dsPIC33FJXXXMCX06/X08/X10 devices offer the
advanced implementation of CodeGuard™ Security.
CodeGuard Security enables multiple parties to
securely share resources (memory, interrupts and
peripherals) on a single chip. This feature helps protect
individual Intellectual Property in collaborative system
designs.
When coupled with software encryption libraries,
CodeGuard Security can be used to securely update
Flash even when multiple IP are resident on the single
chip. The code protection features vary depending on
the actual device implemented. The following sections
provide an overview of these features.
The code protection features are controlled by the
Configuration registers: FBS, FSS and FGS.
23.7
dsPIC33FJXXXMCX06/X08/X10 family digital signal
controllers can be serially programmed while in the end
application circuit. This is simply done with two lines for
clock and data and three other lines for power, ground
and
customers to manufacture boards with unprogrammed
devices and then program the digital signal controller
just before shipping the product. This also allows the
most recent firmware or a custom firmware, to be
programmed. Please refer to the “dsPIC33F/PIC24H
Flash
document for details about ICSP.
Any one out of three pairs of programming clock/data
pins may be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
DS70287C-page 260
Note:
the
JTAG Interface
Code Protection and
CodeGuard™ Security
Programming
In-Circuit Serial Programming
Refer to Section 23. “CodeGuard™
Security” (DS70199) in the “dsPIC33F
Family Reference Manual” for further
information on usage, configuration and
operation of CodeGuard Security.
programming
Specification”
sequence.
This
(DS70152)
allows
23.8
When MPLAB
in-circuit debugging functionality is enabled. This func-
tion allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pin functions.
Any one out of three pairs of debugging clock/data pins
may be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, V
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins.
In-Circuit Debugger
DD
, V
®
SS
ICD 2 is selected as a debugger, the
and the PGECx/PGEDx pin pair. In
© 2009 Microchip Technology Inc.
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