DSPIC33FJ128MC706-I/PT Microchip Technology, DSPIC33FJ128MC706-I/PT Datasheet - Page 76
![IC DSPIC MCU/DSP 128K 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
DSPIC33FJ128MC706-I/PT
Manufacturer Part Number
DSPIC33FJ128MC706-I/PT
Description
IC DSPIC MCU/DSP 128K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
3.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
4.DSPIC33FJ128GP706-IPT.pdf
(371 pages)
Specifications of DSPIC33FJ128MC706-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
64-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
16 KB
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Data Rom Size
4096 B
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128MC706-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ12GP201-ISO PDF datasheet
- DSPIC33FJ64MC506-IPT PDF datasheet #2
- DSPIC33FJ64MC506-IPT PDF datasheet #3
- DSPIC33FJ128GP706-IPT PDF datasheet #4
- Current page: 76 of 340
- Download datasheet (5Mb)
dsPIC33FJXXXMCX06/X08/X10
5.2
The dsPIC33FJXXXMCX06/X08/X10 Flash program
memory array is organized into rows of 64 instructions
or 192 bytes. RTSP allows the user to erase a page of
memory at a time, which consists of eight rows (512
instructions), and to program one row or one word at a
time. Table 26-12 shows typical erase and program-
ming times. The 8-row erase pages and single-row
write rows are edge-aligned, from the beginning of pro-
gram memory, on boundaries of 1536 bytes and 192
bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers in sequential order. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles), because only the buffers are
written.
programming each row.
DS70287C-page 74
RTSP Operation
A
programming
cycle
is
required
for
5.3
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode.
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 26-19) and the value of the FRC Oscillator
Tuning register (see Register 9-4). Use the following
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time and Word
Write Cycle Time parameters (see Table 26-12).
EQUATION 5-1:
For example, if the device is operating at +85°C, the
FRC accuracy will be ±2%. If the TUN<5:0> bits (see
Register 9-4) are set to ‘b111111, the Minimum
Row Write Time is:
and, the Maximum Row Write Time is:
Setting the WR bit (NVMCON<15>) starts the opera-
tion, and the WR bit is automatically cleared when the
operation is finished.
5.4
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 0x55 and 0xAA to the
NVMKEY register. Refer to Section 5.3 “Programming
Operations” for further details.
T
T
RW
RW
------------------------------------------------------------------------------------------------------------------------- -
7.37 MHz
=
=
--------------------------------------------------------------------------------------------- - 1.54ms
7.37 MHz
The
---------------------------------------------------------------------------------------------- 1.48ms
7.37 MHz
Programming Operations
Control Registers
×
processor
(
FRC Accuracy
×
×
(
(
11064 Cycles
11064 Cycles
1 0.02
1
PROGRAMMING TIME
–
+
© 2009 Microchip Technology Inc.
0.02
T
stalls
)
)
×
)%
×
(
(
1 0.00375
1 0.00375
×
–
–
(
(waits)
FRC Tuning
)
)
until
=
=
)%
the
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