ATMEGA644-20PU Atmel, ATMEGA644-20PU Datasheet - Page 228
![IC AVR MCU FLASH 64K 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA644-20PU
Manufacturer Part Number
ATMEGA644-20PU
Description
IC AVR MCU FLASH 64K 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644-20PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN, ATAVRRZUSBSTICK, ATAVRRZ201
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
20MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA644-20PU
Manufacturer:
Atmel
Quantity:
1 930
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19.9.5
19.9.6
228
ATmega644
TWAR – TWI (Slave) Address Register
TWAMR – TWI (Slave) Address Mask Register
of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the
ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7:0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the 2-wire Serial Bus.
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of
TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,
and not needed in the Master modes. In multimaster systems, TWAR must be set in masters
which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an
associated address comparator that looks for the slave address (or general call address if
enabled) in the received serial address. If a match is found, an interrupt request is generated.
• Bits 7:1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
• Bits 7:1 – TWAM: TWI Address Mask
The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can
mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask
bit is set to one then the address match logic ignores the compare between the incoming
address bit and the corresponding bit in TWAR.
detail.
Bit
(0xBA)
Read/Write
Initial Value
Bit
(0xBD)
Read/Write
Initial Value
TWA6
R/W
R/W
7
1
7
0
TWA5
R/W
R/W
6
1
6
0
TWA4
R/W
R/W
5
1
5
0
TWAM[6:0]
TWA3
R/W
R/W
4
1
4
0
Figure 19-22
TWA2
R/W
R/W
3
1
3
0
TWA1
R/W
R/W
shows the address match logic in
2
1
2
0
TWA0
R/W
R/W
1
1
1
0
TWGCE
R/W
R
0
0
0
0
–
2593N–AVR–07/10
TWAMR
TWAR
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