AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet
AT91SAM9M10-CU
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AT91SAM9M10-CU Summary of contents
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... Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input • Package – 324-ball TFBGA, pitch 0.8 mm AT91 ARM Thumb-based Microcontrollers AT91SAM9M10 Preliminary Summary NOTE: This is a summary document. The complete document is available under NDA. For more information, please contact your local Atmel sales office. ...
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... The AT91SAM9M10 supports the latest generation of DDR2 and NAND Flash memory inter- faces for program and data storage. An internal 133 MHz multi-layer bus architecture associated with 37 DMA channels, a dual external bus interface and distributed memory including a 64- KByte SRAM which can be configured as a tightly coupled memory (TCM) sustains the high bandwidth required by the processor and the high speed peripherals ...
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... Block Diagram Figure 2-1. AT91SAM9M10 Block Diagram 6355BS–ATARM–21-Jun-10 PIO AT91SAM9M10 3 ...
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... XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output VBG Bias Voltage Reference for USB PCK0 - PCK1 Programmable Clock Output AT91SAM9M10 4 gives details on the signal names classified by peripheral. Active Type Level Power Supplies Power Power Power ...
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... Input Debug Unit - DBGU Input Output Advanced Interrupt Controller - AIC Input Input PIO Controller - PIOA- PIOB - PIOC - PIOD - PIOE I/O I/O AT91SAM9M10 Reference Voltage Comments Driven at 0V only. 0: The device is in backup mode VDDBU 1: The device is running (not in backup mode). Accept between 0V and VDDBU VDDBU ...
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... Write Signal NRD Read Signal NWE Write Enable NBS0 - NBS3 Byte Mask Signal CFCE1 - CFCE2 CompactFlash Chip Enable CFOE CompactFlash Output Enable CFWE CompactFlash Write Enable CFIOR CompactFlash IO Read AT91SAM9M10 6 Active Reference Type Level (1) I/O (1) I/O (1) I/O I/O VDDIOM0 Output VDDIOM0 ...
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... High Speed Multimedia Card Interface - HSMCIx I/O I/O I/O I/O Output Input Output Input Synchronous Serial Controller - SSCx Output Input I/O I/O I/O I/O AT91SAM9M10 Reference Voltage Comments VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 ...
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... USB Host Port B High Speed Data - DFSDM USB Device Full Speed Data - DFSDP USB Device Full Speed Data + DHSDM USB Device High Speed Data - DHSDP USB Device High Speed Data + AT91SAM9M10 8 Active Type Level AC97 Controller - AC97C Input Output Output Input ...
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... LCD Controller - LCDC Output Output Output Output Output Output Output Output Touch Screen Analog-to-Digital Converter Analog Analog Analog AT91SAM9M10 Reference Voltage Comments (1) MII only, REFCK in RMII (1) MII only (1) (1) ETX0-ETX1 only in RMII (1) MII only (1) RXDV in MII, CRSDV in RMII (1) ...
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... I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Inter- face signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the peripheral multiplexing tables. AT91SAM9M10 10 Active ...
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... Package and Pinout The AT91SAM9M10 is delivered in a 324-ball LFBGA package. 4.1 Mechanical Overview of the 324-ball LFBGA Package Figure 4-1 Figure 4-1. 6355BS–ATARM–21-Jun-10 shows the orientation of the 324-ball LFBGA Package Orientation of the 324-ball LFBGA Package AT91SAM9M10 Bottom VIEW ...
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... TFBGA Package Pinout Table 4-1. AT91SAM9M10 Pinout for 324-ball BGA Package Pin Signal Name Pin A1 PC27 E10 A2 PC28 E11 A3 PC25 E12 A4 PC20 E13 A5 PC12 E14 A6 PC7 E15 A7 PC5 E16 A8 PC0 E17 A9 NWR3/NBS3 E18 A10 NCS0 F1 A11 DQS0 F2 A12 RAS ...
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... Table 4-1. AT91SAM9M10 Pinout for 324-ball BGA Package (Continued) Pin Signal Name Pin C13 D10 H4 C14 D6 H5 C15 D2 H6 C16 GNDIOM H7 C17 A18 H8 C18 A12 H9 D1 XOUT32 H10 D2 PD20 H11 D3 GNDBU H12 D4 VDDBU H13 D5 PC24 H14 D6 PC18 H15 D7 PC13 H16 D8 PC6 ...
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... Power Considerations 5.1 Power Supplies The AT91SAM9M10 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V nominal. • VDDIOM0 pins: Power the DDR2/LPDDR I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical). • ...
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... Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit • TCM Interface 6355BS–ATARM–21-Jun-10 each quarter of the page system flexibility 32-bit data interface (Words) AT91SAM9M10 15 ...
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... Allows Handling of Dynamic Exception Vectors 6.2.1 Matrix Masters The Bus Matrix of the AT91SAM9M10 manages Masters, thus each master can perform an access concurrently with others, depending on whether the slave it accesses is available. Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings ...
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... UDP High Speed RAM LCD User Interface Video Decoder DDR Port 0 DDR Port 1 DDR Port 2 DDR Port 3 External Bus Interface Internal Peripherals Video Decoder is not enabled (VDEC_SEL=0) Video Decoder is enabled (VDEC_SEL=1), AT91SAM9M10 , the ARM instruction and data are DDR Port 0 is dedicated to the video 17 ...
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... LCD User Int. X UDPHS RAM X 1 VDEC X 2 DDR Port DDR Port DDR Port DDR Port EBI X 7 Internal Periph. X AT91SAM9M10 18 Video Mode Configuration Video Decoder LCD + Post Processing DMA MATRIX AT91SAM9M10 Masters to Slaves Access with VDEC_SEL = & 5 USB Host PDC OHCI DMA ...
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... Acting as one AHB Bus Matrix Master • Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. • Next Pointer support, prevents strong real-time constraints on buffer management. 6355BS–ATARM–21-Jun-10 AT91SAM9M10 Masters to Slaves Access with VDEC_SEL = 1 (default & 5 ...
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... SSC1 SSC0 6.4 USB The AT91SAM9M10 features USB communication ports as follows: • 2 Ports USB Host full speed OHCI and High speed EHCI • 1 Device High speed USB Host Port A is directly connected to the first UTMI transceiver. The Host Port B is multiplexed with the USB device High speed and connected to the second UTMI port ...
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... Table 6-7. Instance Name MCI0 SPI0 SPI0 SPI1 SPI1 SSC0 SSC0 SSC1 SSC1 AC97C AC97C MCI1 6355BS–ATARM–21-Jun-10 USB Selection HS HS Transceiver Transceiver EHCI FS OHCI DMA DMA Channel Definition DMA Channel HW T/R interface Number TX/ TX/RX 13 AT91SAM9M10 EN_UDPHS 1 HS USB DMA 21 ...
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... Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins. AT91SAM9M10 22 6355BS–ATARM–21-Jun-10 ...
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... Memories Figure 7-1. AT91SAM9M10 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 256M Bytes 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1/ DDRSDRC1 256M Bytes Chip Select 0x2FFF FFFF 0x3000 0000 EBI ...
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... Internal SRAM The AT91SAM9M10 product embeds a total of 64 Kbytes high-speed SRAM split in 4 blocks of 16 KBytes connected to one slave of the matrix. After reset and until the Remap Command is performed, the four SRAM blocks are contiguous and only accessible at address 0x00300000. ...
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... Note: All the memory blocks can always be seen at their specified base addresses that are not concerned by these parameters. The AT91SAM9M10 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect ...
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... Switch the main clock to the new value 7.3 External Memories The AT91SAM9M10 features a Multi-port DDR2 Interface and an External Bus Interface allow- ing to connect to a wide range of external memories and to any parallel peripheral. 7.3.1 DDRSDRC0 Multi-port DDRSDR Controller Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Mini- mizes Transaction Latency ...
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... Byte Write or Byte Select Lines – Asynchronous read in Page Mode supported ( 32-byte page size) • Multiple device adaptability – Control signals programmable setup, pulse and hold time for each Memory Bank 6355BS–ATARM–21-Jun-10 Average Latency of Transactions) AT91SAM9M10 TM M support 27 ...
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... ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes AT91SAM9M10 28 Average Latency of Transactions) detected erroneous pages 6355BS– ...
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... All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KB. Figure 8-1 on page 30 Figure 7-1 on page 23 peripherals. 6355BS–ATARM–21-Jun-10 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller AT91SAM9M10 29 ...
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... System Controller Block Diagram Figure 8-1. AT91SAM9M10 System Controller Block Diagram periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset backup_nreset SHDN WKUP RC OSC SLOW XIN32 CLOCK XOUT32 OSC XIN 12MHz ...
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... MHz input, the only limitation being the lowest input frequency shall be higher or equal to 2 MHz. The USB Device and Host HS Clocks are provided by a the dedicated UTMI PLL (UPLL) embedded in the UTMI macro. 6355BS–ATARM–21-Jun-10 AT91SAM9M10 31 ...
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... Figure 8-2. 8.6 Slow Clock Selection The AT91SAM9M10 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768 Hz crystal oscillator can be bypassed, by setting the bit OSC32BYP, to accept an external slow clock on XIN32. The internal RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1 respec- tively RCEN bit and OSC32EN bit in the system controller user interface ...
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... Enable the internal RC oscillator by setting the bit RCEN to 1. • Wait internal RC Startup Time for clock stabilization (software loop). 6355BS–ATARM–21-Jun-10 Slow Clock Clock Generator On Chip RC OSC Slow Clock XIN32 Oscillator XOUT32 AT91SAM9M10 RCEN Slow Clock SLCK OSCSEL OSC32EN OSC32BYP 33 ...
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... Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery AT91SAM9M10 34 DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK). ...
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... Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10) • System Input clock is UPLLCK, Prescaler is 2, PCK is 240 MHz • MDIV is ‘01’, MCK is 120 MHz • Only LP-DDR can be used 120 MHz 6355BS–ATARM–21-Jun-10 AT91SAM9M10 Power Management Controller Block Diagram USBS USBDIV+1 /1,/2 UPLLCK Prescaler /1,/2,/4, ...
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... Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) – Programmable Edge-triggered or Level-sensitive Internal Sources – Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive AT91SAM9M10 36 Controller 6355BS–ATARM–21-Jun-10 ...
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... Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from 8.15 Chip Identification The AT91SAM9M10 Chip ID is defined in the Debug Unit Chip ID Register and Debug Unit Chip ID Extension Register. • Chip ID: 0x819B05A2 • Ext ID: 0x00000002 • ...
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... Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write AT91SAM9M10 38 6355BS–ATARM–21-Jun-10 ...
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... VDEC 31 AIC 6355BS–ATARM–21-Jun-10 Figure 7-1, the Peripherals are mapped in the upper 256 Mbytes of the address defines the Peripheral Identifiers of the AT91SAM9M10. A peripheral identifier is Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A, Parallel I/O Controller B Parallel I/O Controller C ...
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... Peripheral ID. However, there is no clock control associated with these peripheral IDs. 9.4 Peripheral Signals Multiplexing on I/O Lines The AT91SAM9M10 features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which mul- tiplexes the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “ ...
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... I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 SCK3 I/O VDDIOP0 RTS3 I/O VDDIOP0 CTS3 I/O VDDIOP0 PWM3 I/O VDDIOP0 TIOB2 I/O VDDIOP0 ETXER I/O VDDIOP0 ERXCK I/O VDDIOP0 ECRS I/O VDDIOP0 ECOL I/O VDDIOP0 PCK0 I/O VDDIOP0 AT91SAM9M10 Function Comments 41 ...
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... ISI_D1 PB22 ISI_D2 PB23 ISI_D3 PB24 ISI_D4 PB25 ISI_D5 PB26 ISI_D6 PB27 ISI_D7 PB28 ISI_PCK PB29 ISI_VSYNC PB30 ISI_HSYNC PB31 ISI_MCK AT91SAM9M10 42 Reset Power Peripheral B State Supply I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 ...
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... I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 AT91SAM9M10 Function Comments 43 ...
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... TIOA1 PD22 TIOA2 PD23 TCLK0 PD24 SPI0_NPCS1 PD25 SPI0_NPCS2 PD26 PCK0 PD27 PCK1 PD28 TSADTRG PD29 TCLK1 PD30 TIOB0 PD31 TIOB1 AT91SAM9M10 44 Reset Power Peripheral B State Supply PWM3 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O ...
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... I/O VDDIOP1 LCDD15 I/O VDDIOP1 LCDD18 I/O VDDIOP1 LCDD19 I/O VDDIOP1 LCDD20 I/O VDDIOP1 LCDD21 I/O VDDIOP1 LCDD22 I/O VDDIOP1 LCDD23 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 PCK1 I/O VDDIOP1 AT91SAM9M10 Function Comments 45 ...
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... Asynchronous Mode stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first AT91SAM9M10 46 peripherals Sensors and data per chip select ...
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... Variable sampling rate AC97 Codec Interface (48KHz and below) 10.6 Timer Counter (TC) • Three 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation 6355BS–ATARM–21-Jun-10 AT91SAM9M10 2 S, TDM Buses, Magnetic Card Reader,...) 47 ...
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... Root Hub Integrated with 2 Downstream USB Ports • Shared 10.10 USB High Speed Device Port (UDPHS) • USB V2.0 high-speed compliant, 480 MBits per second • Embedded USB V2.0 UTMI+ high-speed transceiver shared with UHP HS. AT91SAM9M10 48 Embedded USB Transceivers 6355BS–ATARM–21-Jun-10 ...
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... Automatic wakeup on trigger and back to sleep mode after conversions of all 10.13 Ethernet 10/100 MAC (EMAC) • Compatibility with IEEE Standard 802.3 • 10 and 100 MBits per second data throughput capability • Full- and half-duplex operations 6355BS–ATARM–21-Jun-10 enabled channels AT91SAM9M10 49 ...
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... User enabled auto-reloading of source, destination and control registers from initially – Auto-loading of source, destination and control registers from system memory at end – Unaligned system address to data transfer width supported in hardware • Channel Buffering AT91SAM9M10 50 lists transfer. Writing a stream of data into non-contiguous fields in system memory ...
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... YCbCr to RGB conversion • Dithering • Deinterlacing • Programmable alpha channel • Alpha blending • De-blocking filter for MPEG-4 simple profile/H.263 6355BS–ATARM–21-Jun-10 to control the flow of a DMA transfer in place of a hardware handshaking interface completion, Single/Multiple transaction completion or Error condition AT91SAM9M10 51 ...
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... Image cropping / digital zoom • Picture in picture • Supported display size for picture in picture • Image rotation AT91SAM9M10 52 6355BS–ATARM–21-Jun-10 ...
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... Mechanical Characteristics 11.1 Package Drawings Figure 11-1. 324-ball TFBGA Package Drawing 6355BS–ATARM–21-Jun-10 AT91SAM9M10 53 ...
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... AT91SAM9M10 Ordering Information Table 12-1. AT91SAM9M10 Ordering Information Ordering Code AT91SAM9M10-CU AT91SAM9M10 54 Package Package Type TFBGA324 Green Temperature Operating Range Industrial -40°C to 85°C 6355BS–ATARM–21-Jun-10 ...
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... Section 10.16 “True Random Number Generator (TRNG)” 6355BS ‘11-layer --> ‘12-layer’ in New Figure 11-1 “324-ball TFBGA Package Drawing” Section 7.3 “External Memories” 6355AS First issue 6355BS–ATARM–21-Jun-10 added. added. Section 6.2 “Bus Matrix” . reorganized. AT91SAM9M10 Change Request Ref. RFO 7172 7171 6954 RFO 55 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...